LT3435EFE#PBF Linear Technology, LT3435EFE#PBF Datasheet - Page 19

• Manufacturer Part Number: LT3435EFE#PBF
• Description: IC REG SW HV 3A 500KHZ 16-TSSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LT3435EFE#PBF

• Internal Switch(s): Yes
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 1.25 ~ 54 V
• Current - Output: 3A
• Frequency - Switching: 500kHz
• Voltage - Input: 3.3 ~ 60 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Primary Input Voltage: 60V
• No. Of Outputs: 1
• Output Voltage: 68V
• Output Current: 2.4A
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +125°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
threshold during normal operation, the C
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
100k TO V
500mV/DIV
500mV/DIV
2V/DIV
V
V
SHDN
OUT
V
PG
CT
IN
PG at 80% V
V
OUT
LT3435
LT3435
Figure 9. Power Good
U
PGFB
PGFB
Disconnect at 80% V
with 100ms Delay
V
V
PG
PG
FB
FB
C
C
IN
IN
T
T
U
OUT
TIME (10ms/DIV)
T
= 0.1µF. The PGOOD pin has
with 100ms Delay
0.27µF
0.27µF
200k
W
200k
153k
12k
100k
153k
12k
100k
OUT
T
C
C
Figure 10. Power Good Circuits
pin will be
OUT
OUT
3435 F09
V
U
OUT
= 3.3V
V
OUT
= 3.3V
V
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT3435 Power Good circuitry. Figure 10
shows several different configurations for the LT3435
Power Good circuitry.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
PG at V
OUT
LT3435
LT3435
Disconnect 3.3V Logic Signal
PGFB
PGFB
IN
with 100µs Delay
V
V
PG
PG
FB
C
FB
C
IN
IN
T
T
> 4V with 100ms Delay
511k
200k
0.27µF
270pF
200k
200k
165k
100k
866k
100k
3435 F10
C
OUT
C
V
OUT
OUT
= 3.3V
V
OUT
= 12V
LT3435
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