BD9775FV-E2 Rohm Semiconductor, BD9775FV-E2 Datasheet - Page 12

• Manufacturer Part Number: BD9775FV-E2
• Description: IC REG SW STEP DOWN HE 28-SSOP
• Manufacturer: Rohm Semiconductor
• Type: Step-Down (Buck)r

Specifications of BD9775FV-E2

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Current - Output: 400mA
• Frequency - Switching: 100kHz
• Voltage - Input: 6 ~ 30 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Power - Output: 640mW
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: BD9775FV-E2TR

（9）MOSFET selection
（10）Schottky barrier diode selection
（11）Sequence function
●Circuit diagram
Vo1
VCC VREG5
V
V
GSM1
GSM2
OUTH1 BOOT1 VCC BOOT2
SW1
OUTL1
DGND1
FB1
COMP1
SS1
DET2
V
V
CC
CC
STB
V
V
DS
DS
Fig-33
Fig-35
EN1
Fig-34
EN2 GND
V
I
L
R
COMP2
DGND2
OUTL2
DET1
OUTH2
SW2
SS2
FB2
Vo
VREG5
Vo
12/29
Vo2
FET uses Nch MOS
・V
・V
・V
・Allowable current＞voltage current + ripple current
・ Reverse voltage V
・ Allowable current＞voltage current + ripple current
・ The shoot-through may happen when the input parasitic
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for highest
capacitance of FET is extremely big or the Duty ratio is less
than or equal to 10%. Less than or equal to 1000pF input
parasitic capacitance is recommended. Please confirm
operation on the actual application since this character is
affected by PCB layout and components.
With EN1, 2 at ”H” level, when EN1 goes ”L”,
Vo1 turns OFF, but Vo2 output continues.
DS
GSM1
GSM2
●Timing chart
efficiency
＞Vcc
DET2
DET1
EN1
EN2
SS1
SS2
FB1
FB2
Vo1
Vo2
＞BOOT-SW interval voltage
＞VREG5
With EN1,2 at “H” level, if
Vo1 starts at 76% or more of
voltage setting, DET goes
open and SS1 is asserted,
starting Vo2 output.
0.61V
over 76%
R
＞Vcc
under 70%
Fig-36
A
0.56V
With EN2 set ”L”, if Vo2
goes below 70% the voltage
setting, DET2 shorts and SS1
is asserted, turning Vo1 OFF
When EN1 stays ”H” and EN2 returns to ”H”, DET1 is in
open state; thus SS2 is asserted, and Vo2 output starts.
If Vo2 is 76% of the voltage setting or higher, DET2 goes
open and SS1 is asserted, starting Vo1 output.
0.61V
over 76%
A
Same as “A” at left
0.56V
over 70%