ICL7660CBAZ-T Intersil, ICL7660CBAZ-T Datasheet - Page 6

• Manufacturer Part Number: ICL7660CBAZ-T
• Description: IC VOLTAGE CONVERTER CMOS 8-SOIC
• Manufacturer: Intersil
• Type: Switched Capacitor (Charge Pump), Invertingr

Specifications of ICL7660CBAZ-T

• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Voltage - Input: 1.5 ~ 10 V
• Operating Temperature: 0°C ~ 70°C
• Number Of Outputs: 1
• Internal Switch(s): Yes
• Frequency - Switching: 10kHz
• Synchronous Rectifier: No
• Package: 8SOIC N
• Function: Inverting/Step Up
• Output Voltage: -1.5 to -10|18.6(Max) V
• Output Current: 45(Max) mA
• Rohs Compliant: YES
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -

Typical Performance Curves
NOTE:
NOTE: For large values of C
Detailed Description
The ICL7660 and ICL7660A contain all the necessary
circuitry to complete a negative voltage converter, with the
exception of 2 external capacitors which may be inexpensive
10µF polarized electrolytic types. The mode of operation of
the device may be best understood by considering Figure
12, which shows an idealized negative voltage converter.
Capacitor C
when switches S
and S
half cycle of operation, switches S
S
V+ volts. Charge is then transferred from C
the voltage on C
no load on C
more closely than existing non-mechanical circuits.
6. These curves include in the supply current that current fed directly into the load R
1
FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT
and S
+2
+1
supply current goes directly to the positive side of the load, and the other half, through the ICL7660/ICL7660A, to the negative side of the load.
Ideally, V
-1
-2
0
4
0
are open during this half cycle.) During the second
T
V+ = 2V
3
A
open, thereby shifting capacitor C
= 25
1
OUT
1
2
CURRENT
is charged to a voltage, V+, for the half cycle
. The ICL7660 approaches this ideal situation
°C
2
∼
1
is exactly V+, assuming ideal switches and
2V
and S
2
IN
, I
LOAD CURRENT I
S
3
∼
OSC
3
are closed. (Note: Switches S
2I
L
6
, so V
(>1000pF) the values of C
4
2
IN
and S
10µF
C
x I
L
1
5
(mA)
S
+
-
SLOPE 150Ω
4
∼
FIGURE 11. ICL7660, ICL7660A TEST CIRCUIT
1
are closed, with
(Test Circuit of Figure 11) (Continued)
V
1
to C
OUT
6
negatively by
1
2
3
4
2
x I
such that
ICL7660, ICL7660A
L
.
7
ICL7660A
1
ICL7660
and C2 should be increased to 100µF.
2
8
8
7
6
5
(NOTE)
In the ICL7660 and ICL7660A, the 4 switches of Figure 12
are MOS power switches; S
S
this approach is that in integrating the switches, the
substrates of S
with respect to their sources, but not so much as to degrade
their “ON” resistances. In addition, at circuit start-up, and
under output short circuit conditions (V
voltage must be sensed and the substrate bias adjusted
accordingly. Failure to accomplish this would result in high
power losses and probable device latchup.
This problem is eliminated in the ICL7660 and ICL7660A by a
logic network which senses the output voltage (V
with the level translators, and switches the substrates of S
S
C
10µF
3
4
FIGURE 10. SUPPLY CURRENT AND POWER CONVERSION
OSC
C
to the correct level to maintain necessary reverse bias.
and S
100
2
90
80
70
60
50
40
30
20
10
0
+
-
L
0
from the V+ (See Figure 11). Thus, approximately half the
4
are N-Channel devices. The main difficulty with
R
1.5
EFFICIENCY AS A FUNCTION OF LOAD
CURRENT
I
I
L
L
S
3
and S
V+
LOAD CURRENT I
(+5V)
-V
3.0
OUT
4
P
must always remain reverse biased
EFF
1
4.5
T
V+ = 2V
is a P-Channel device and S
A
= 25
L
°C
6.0
(mA)
OUT
7.5
= V+), the output
I+
OUT
October 10, 2005
9.0
) together
20.0
18.0
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0
FN3072.7
3
and
2
,