ICL7660CBAZ-T Intersil, ICL7660CBAZ-T Datasheet - Page 9

• Manufacturer Part Number: ICL7660CBAZ-T
• Description: IC VOLTAGE CONVERTER CMOS 8-SOIC
• Manufacturer: Intersil
• Type: Switched Capacitor (Charge Pump), Invertingr

Specifications of ICL7660CBAZ-T

• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Voltage - Input: 1.5 ~ 10 V
• Operating Temperature: 0°C ~ 70°C
• Number Of Outputs: 1
• Internal Switch(s): Yes
• Frequency - Switching: 10kHz
• Synchronous Rectifier: No
• Package: 8SOIC N
• Function: Inverting/Step Up
• Output Voltage: -1.5 to -10|18.6(Max) V
• Output Current: 45(Max) mA
• Rohs Compliant: YES
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -

every cycle. In a typical application where f
C = C
R
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
R
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f
increase in switching frequency or filter capacitance ineffective.
Typical electrolytic capacitors may have ESRs as high as 10Ω.
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2 voltages, A and B, as shown in
Figure 14. Segment A is the voltage drop across the ESR of
C
flow into C
flowing out of C
2• I
B is the voltage change across C
the cycle when C
is l
of these voltage drops:
Again, a low ESR capacitor will reset in a higher
performance output.
Paralleling Devices
Any number of ICL7660 and ICL7660A voltage converters
may be paralleled to reduce output resistance. The reservoir
capacitor, C
its own pump capacitor, C
would be approximately:
R
R
R
V
O
O/
2
O
O
OUT
RIPPLE
OUT
at the instant it goes from being charged by C
OUT
≅ 46 + 20 + 5 (ESR
≅
≅
≅ 46 + 20 + 5 (ESR
≅
1
2 (23) +
2 (23) +
=
= C
, hence the total drop is 2• I
• t2/C
[
2
2
) to being discharged through the load (current
R
2
= 10µF:
, serves all devices while each device requires
OUT
2
2 (f
V. The peak-to-peak ripple voltage is the sum
n (number of devices)
2
(5 • 10
(5 • 10
). The magnitude of this current change is
2
PUMP
(of ICL7660/ICL7660A)
supplies current to the load. The drop at B
1
3
3
1
1
) (C2)
) (10-
) (10
C
C
)
)
1
-5
. The resultant output resistance
5
)
)
+ 2 (ESR
9
PUMP
PUMP
+ 4 (ESR
+ 4 (ESR
2
OUT
during time t
• C
• C
C2
C1
C1
1
1
)
• eSR
) term, rendering an
) term, rendering an
]
) + ESR
) + ESR
OSC
I
OUT
C2
= 10kHz and
2
V. Segment
C2
C2
, the half of
1
(current
ICL7660, ICL7660A
Cascading Devices
The ICL7660 and ICL7660A may be cascaded as shown to
produced larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
and ICL7660A R
Changing the ICL7660/ICL7660A Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an
external clock, as shown in Figure 17. In order to prevent
possible device latchup, a 1kΩ resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency using
TTL logic, the addition of a 10kΩ pullup resistor to V+ supply
is required. Note that the pump frequency with external
clocking, as with internal clocking, will be
frequency. Output transitions occur on the positive-going
edge of the clock.
It is also possible to increase the conversion efficiency of the
ICL7660 and ICL7660A at low load levels by lowering the
oscillator frequency. This reduces the switching losses, and is
shown in Figure 18. However, lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C
this is overcome by increasing the values of C
same factor that the frequency has been reduced. For
example, the addition of a 100pF capacitor between pin 7
(OSC) and V+ will lower the oscillator frequency to 1kHz from
its nominal frequency of 10kHz (a multiple of 10), and thereby
necessitate a corresponding increase in the value of C
C
OUT
2
10µF
(from 10µF to 100µF).
= -n (V
+
-
FIGURE 17. EXTERNAL CLOCKING
IN
),
1
2
3
4
OUT
ICL7660A
ICL7660
values.
1
) and reservoir (C
8
7
6
5
+
-
1kΩ
V+
10µF
1
/
2
2
1
of the clock
) capacitors;
and C
V
OUT
October 10, 2005
V+
CMOS
GATE
2
1
FN3072.7
by the
and