MT36VDDF25672Y-335D2 Micron Technology Inc, MT36VDDF25672Y-335D2 Datasheet - Page 31

• Manufacturer Part Number: MT36VDDF25672Y-335D2
• Description: MODULE SDRAM DDR 2GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF25672Y-335D2

• Memory Type: DDR SDRAM
• Memory Size: 2GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.24A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 23: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
PARAMETER/CONDITION
PARAMETER/CONDITION
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Output Low Voltage: I
Input Leakage Current: V
Output Leakage Current: V
Standby Current:
Power Supply Current, READ:
SCL clock frequency = 100 KHz
Powr Supply Current, WRITE:
SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
OUT
IN
= 3mA
OUT
SS
SS
= GND to V
; V
; V
= GND to V
DDSPD
DDSPD
= +2.3V to +3.6V
= +2.3V to +3.6V
DD
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
31
SYMBOL
V
DDSPD
I
V
I
V
V
I
CC
I
CC
I
LO
SB
OL
LI
IH
IL
W
R
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
F
R
I
1GB, 2GB (x72, ECC, DR)
V
DDSPD X
MIN
0.10
0.05
-0.6
2.3
1.6
0.4
184-PIN DDR RDIMM
2
–
MIN
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0.7
0
MAX
©2004 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
50
10
V
V
DDSPD
DDSPD
MAX
3.6
0.4
3
3
4
1
3
UNITS
+ 0.5
x 0.3
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
NOTES
UNITS
mA
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V