SD020EVK National Semiconductor, SD020EVK Datasheet - Page 10

• Manufacturer Part Number: SD020EVK
• Description: BOARD EVALUATION CLC020
• Manufacturer: National Semiconductor

Specifications of SD020EVK

• Design Resources: CLC020 Board Schematic
• Main Purpose: Interface, Serializer
• Utilized Ic / Part: CLC020
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Not Compliant

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Application Information
A typical application circuit for the CLC020 is shown in
Figure 7. This circuit demonstrates the capabilities of the
CLC020 and allows its evaluation in a variety of configura-
tions. An assembled demonstration board with more com-
prehensive evaluation options is available, part number
APPLICATION CIRCUIT
Several different input and output drive and loading options
can be constructed on the SD020EVK application circuit
board, Figure 8. Pin headers are provided for input cabling
and control signal access. The appropriate value resistor
packs, 220 and 330Ω for TTL or 50Ω for signal sources
requiring such loading, should be installed at RP1-4 before
applying input signals.
The board’s outputs may be DC interfaced to PECL inputs by
first installing 124Ω resistors at R1B and R2B, changing R1A
and R2A to 187Ω and replacing C1 and C2 with short
circuits. The PECL inputs should be directly connected to J1
and J2 without cabling. If 75Ω cabling is used to connect the
CLC020 to the PECL inputs, the voltage dividers used on the
CLC020 outputs must be removed and re-installed on the
circuit board where the PECL device is mounted. This will
FIGURE 7. Typical Application Circuit
10
SD020EVK. The board may be ordered through any of Na-
tional’s sales offices. Complete circuit board layouts and
schematics, for the SD020EVK are available on National’s
WEB site in the application information for this device. For
latest information, please see: www.national.com/appinfo/
interface
provide correct termination for the cable and biasing for both
the CLC020’s outputs and the PECL inputs. It is most impor-
tant to note that a 75Ω or equivalent DC loading (measured
with respect to the negative supply rail) must always be
installed at both of the CLC020’s SDO outputs to obtain
proper signal levels from device. When using 75Ω Thevenin-
equivalent load circuits, the DC bias applied to the SDO
outputs should not exceed +3V with respect to the negative
supply rail. Serial output levels should be reduced to 400
mV
The Test Out output is intended for monitoring by equipment
presenting high impedance loading (
ing the Lock Detect output, the attached monitoring circuit
should present a DC resistance greater than 5 kΩ so that
Lock Detect indicator operation is not affected.
p-p
by changing R
REF
to 3.4 kΩ.
>
500Ω). When monitor-
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