SD020EVK National Semiconductor, SD020EVK Datasheet - Page 12

• Manufacturer Part Number: SD020EVK
• Description: BOARD EVALUATION CLC020
• Manufacturer: National Semiconductor

Specifications of SD020EVK

• Design Resources: CLC020 Board Schematic
• Main Purpose: Interface, Serializer
• Utilized Ic / Part: CLC020
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Not Compliant

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Application Information
is ground). Configure the SD020EVK to operate in the NTSC
colour bars, BIST mode. Configure the VM700T to make the
jitter measurement in the jitter FFT mode at the frame rate
with 1kHz filter bandwidth and Hanning window. Configure
the setup as shown in Figure 9. Switch the test equipment on
(from standby mode) and allow all equipment temperatures
stabilize per manufacturer’s recommendation. Measure the
jitter value after allowing the instrument’s reading to stabilize
(about 1 minute). Consult the VM700T Video Measurement
Set Option 1S Serial Digital Measurements User Manual
(document number 071-0074-00) for details of equipment
operation.
FIGURE 10. ECL-to-TTL/CMOS level converter/amplifer
(Continued)
FIGURE 9. Jitter Test Circuit
12
The VM700T measurement system’s jitter floor specification
at 270Mbps is given as 200ps
actual components from 50Hz to 1MHz and 200ps +60%,
-30% of actual components from 1MHz to 10MHz. To obtain
the actual residual jitter of the CLC020, a root-sum-square
adjustment of the jitter reading must be made to compensate
for the measurement system’s jitter floor specification. For
example, if the jitter reading is 250ps, the CLC020 residual
jitter is the square root of (250
accuracy limits of the reading as given above apply.
±
20% (100ps
2
− 200
10091710
2
) = 150ps. The
±
5% typical) of
10091713