SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet - Page 32

• Manufacturer Part Number: SI3216PPQ1-EVB
• Description: BOARD EVAL W/SI3201 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3216PPQ1-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3216
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3216
2.1.6. Loop Closure Detection
A loop closure event signals that the terminal equipment
has gone off-hook during On-Hook Transmission or On-
Hook Active states. The ProSLIC performs loop closure
detection digitally using its on-chip monitor A/D
converter. The functional blocks required to implement
loop closure detection are shown in Figure 18. The
primary input to the system is the Loop Current Sense
value provided in the LCS register (direct Register 79).
The LCS value is processed in the Input Signal
Processor when the ProSLIC is in the On-Hook
Transmission or On-Hook Active Linefeed state, as
indicated by the Linefeed Shadow register, LFS[2:0]
(direct Register 64). The data then feeds into a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The output of the low-pass filter is compared to a
programmable threshold, LCRT (indirect Register 15).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has
been satisfied, the LCR bit will be set to indicate that a
valid loop closure has occurred. A loop closure interrupt
is generated if enabled by the LCIE bit (direct
Register 22). Table 25 lists the registers that must be
written or monitored to correctly detect a loop closure
condition.
2.1.7. Loop Closure Threshold Hysteresis
Programmable hysteresis to the loop closure threshold
can be enabled by setting HYSTEN = 1 (direct
Register 108, bit 0). The hysteresis is defined by LCRT
(indirect Register 15) and LCRTL (indirect Register 66),
which set the upper and lower bounds, respectively.
32
LCS
LVS
Processor
LFS
Signal
Input
LCVE
ISP_OUT
Figure 18. Loop Closure Detection
HYSTEN
Digital
NCLR
LPF
Loop Closure
LCRT
Threshold
LCRTL
Rev. 1.0
+
–
Loop Closure
Interrupt Pending
Loop Closure
Interrupt Enable
Loop Closure Threshold
Loop Closure
Threshold—Lower
Loop Closure Filter
Coefficient
Loop Closure Detect
Status (monitor only)
Loop Closure Detect
Debounce Interval
Hysteresis Enable
Voltage-Based Loop
Closure
2.1.8. Voltage-Based Loop Closure Detection
An optional voltage-based loop closure detection mode
is enabled by setting LCVE = 1 (direct Register 108,
bit 2). In this mode, the loop voltage is compared to the
loop
represents a minimum voltage threshold instead of a
maximum current threshold. If hysteresis is also
enabled, then LCRT represents the upper voltage
boundary and LCRTL represents the lower voltage
boundary for hysteresis. Although voltage-based loop
closure detection is an option, the default current-based
loop closure detection is recommended.
Parameter
closure
Table 25. Register Set for Loop
Debounce
Filter
LCDI
threshold
Closure Detection
LCR
NCLR[12:0] Indirect Reg. 22
LCRTL[5:0] Indirect Reg. 66
LCRT[5:0]
LCDI[6:0]
HYSTEN
Register
register
LCVE
Interrupt
LCIP
LCIE
LCR
Logic
LCIE
(LCRT),
LCIP
Direct Reg. 108
Direct Reg. 108
Indirect Reg.15
Direct Reg. 22
Direct Reg. 68
Direct Reg. 69
Direct Reg.19
Location
which