SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet - Page 46

• Manufacturer Part Number: SI3216PPQ1-EVB
• Description: BOARD EVAL W/SI3201 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3216PPQ1-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3216
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3216
subscriber loop via the ITIPP and IRINGP pins through
an off-chip current buffer (I
using transistors Q1 and Q2 (see Figure on page 22).
G
The ProSLIC also provides a means of compensating
for degraded subscriber loop conditions involving
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
When 600 + 1 µF or 900 + 2.16 µF impedances are
selected, an internal reference resistor is removed from
the impedance synthesis circuit to accommodate an
external resistor, R
circuit as shown in Figure 25.
2.7. Clock Generation
The ProSLIC generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz, or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined via a counter clocked by PCLK. The
three-bit ratio information is automatically transferred
into an internal register, PLL_MULT, following a reset of
the ProSLIC. The internal PLL_MULT register is used to
control the internal PLL, which multiplies PCLK as
needed to generate the 16.384 MHz rate needed to run
the internal filters and other circuitry.
The PLL clock synthesizer settles very quickly following
powerup. However, the settling time depends on the
PCLK frequency and it can be approximately predicted
by the following equation:
46
Figure 25. R
m
For 600 + 1 F, R
For 900 + 2.16 F, R
is referenced to an off-chip resistor (R
to TIP
to RING
ZREF
ZREF
T
ZREF
SETTLE
External Resistor Placement
C3
C4
ZREF
= 12 k and C3, C4 = 100 nF
, inserted into the application
= 18 k and C3, C4 = 220 nF
BUF
R
=
ZREF
---------------- -
F
R8
R9
), which is implemented
PCLK
64
STIPAC
SRINGAC
15
Si3216
).
Rev. 1.0
2.8. Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:










The interface to the interrupt logic consists of six
registers. Three interrupt status registers contain 1 bit
for each of the above interrupt functions. These bits are
set when an interrupt is pending for the associated
resource. Three interrupt enable registers also contain 1
bit for each interrupt function. In the case of the interrupt
enable registers, the bits are active high. Refer to the
appropriate
operational details of the interrupt functions.
When a resource reaches an interrupt condition, it
signals an interrupt to the interrupt control block. The
interrupt control block then sets the associated bit in the
interrupt status register if the enable bit for that interrupt
is set. The INT pin is an open-drain output and a NOR
of the bits of the interrupt status registers. Therefore, if a
bit in the interrupt status registers is asserted, IRQ
asserts low. Upon receiving the interrupt, the interrupt
handler should read interrupt status registers to
determine which resource is requesting service. To
clear a pending interrupt, write the desired bit in the
appropriate interrupt status register to 1. Writing a 0 has
no effect. This provides a mechanism for clearing
individual
simultaneously. While the interrupt status registers are
non-zero, the INT pin will remain asserted.
2.9. Serial Peripheral Interface
The control interface to the ProSLIC is a 4-wire interface
modeled after commonly-available microcontroller and
serial peripheral devices. The interface consists of a
clock (SCLK), chip select (CS), serial data input (SDI),
and serial data output (SDO). Data is transferred a byte
at a time with each register access consisting of a pair
of byte transfers. Figures 26 and 27 illustrate read and
write operation in the SPI bus.
The first byte of the pair is the command/address byte.
The MSB of this byte indicates a register read when 1
and a register write when 0. The remaining seven bits of
Loop current/ring ground detected
Ring trip detected
Power alarm
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Indirect register access complete
bits
functional
when
multiple
description
interrupts
section
occur
for