SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet - Page 45

• Manufacturer Part Number: SI3216PPQ1-EVB
• Description: BOARD EVAL W/SI3201 INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3216PPQ1-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3216
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.5.2. Receive Path
In the receive path, digital voice is expanded from µ/A-
law if enabled. DACG is the receive path programmable
gain amplifier which can be programmed from –  dB to
6 dB. A 16-bit signal is then provided to a D/A converter.
The resulting analog signal is amplified by the analog
receive amplifier, ARX, which has the following gain
options: mute, –3.5, 0, and 3.5 dB. It is then applied at
the input of the transconductance amplifier (Gm), which
drives the off-chip current buffer (I
2.5.3. Companding
The ProSLIC supports both µ-255 law and A-law
companding formats when narrowband mode is
selected. µ-255 law is more commonly used in North
America and Japan, while A-law is used primarily in
Europe. Data format is selected using the PCMF
register. Tables 32 and 33 define µ-law and A-law
formats, respectively.
The dominant source of distortion and noise in both the
transmit and receive paths is the quantization noise
introduced by the µ-law or the A-law compression
process. Figure 3 on page 11 specifies the minimum
signal-to-noise and distortion ratio for either path for a
sine wave input of 200 Hz to 3400 Hz.
Both µ-law and A-law speech encoding allow the audio
codec to transfer and process audio signals larger than
0 dBm0 without clipping. The maximum PCM code is
generated for a µ-law encoded sine wave of 3.17 dBm0
or an A-law encoded sine wave of 3.14 dBm0. The
ProSLIC overload clipping limits are driven by the PCM
encoding process. Figure 4 on page 11 shows the
acceptable limits for the analog-to-analog fundamental
power transfer function, which bounds the behavior of
ProSLIC.
2.5.4. Transhybrid Balance
The ProSLIC provides programmable transhybrid
balance with gain block H. (See Figure 24.) In the ideal
case where the synthesized SLIC impedance exactly
matches
transhybrid balance should be set to subtract a –6 dB
level from the transmit path signal. The transhybrid
balance gain can be adjusted from –2.77 dB to
+4.08 dB around the ideal setting of –6 dB by
programming the HYBA[2:0] bits of the Hybrid Control
register (direct Register 11). Adjusting any of the analog
or digital gain blocks does not require any modification
of the transhybrid balance gain block, as the transhybrid
gain is subtracted from the transmit path signal prior to
any gain adjustment stages. The transhybrid balance
can also be disabled, if desired, using the appropriate
register setting.
the
subscriber
loop
BUF
).
impedance,
the
Rev. 1.0
2.5.5. Loopback Testing
Four loopback test options are available in the ProSLIC:




2.6. Two-Wire Impedance Matching
The ProSLIC provides on-chip programmable two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600  will be loaded into the TISS
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC), a
switched
transconductance amplifier (G
creates the real portion, and XAC creates the imaginary
portion of the ac impedance. G
that models the desired impedance value to the
subscriber loop. The differential ac current is fed to the
The full analog loopback (ALM2) tests almost all the
circuitry of both the transmit and receive paths. The
transmit data stream is fed back serially to the input
of the receive path expander. (See Figure 24.) The
signal path starts with the analog signal at the input
of the transmit path and ends with an analog signal
at the output of the receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 24.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows testing of the analog signal
processing circuitry of the ProSLIC completely
independently of any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path is fed back to
the input of the transmit path by way of the hybrid
filter path. (See Figure 24.) The signal path starts
with PCM data input to the receive path and ends
with PCM data at the output of the transmit path.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with PCM data
input to the receive path and ends with PCM data at
the output of the transmit path. This loopback option
allows testing of the ProSLIC digital signal
processing circuitry completely independently of any
analog signal processing activity.
capacitor
network
m
m
) (See Figure 24.) RAC
then creates a current
(XAC),
Si3216
and
45
a