EVK-DS40MB200 National Semiconductor, EVK-DS40MB200 Datasheet
EVK-DS40MB200
Specifications of EVK-DS40MB200
Related parts for EVK-DS40MB200
EVK-DS40MB200 Summary of contents
Page 1
... All drivers are internally ter- minated with 50Ω Functional Block Diagram Note: All CML inputs and outputs must be AC coupled for optimal performance. © 2009 National Semiconductor Corporation DS40MB200 Features ■ 1– 4 Gbps low jitter operation ■ Fixed input equalization ■ ...
Page 2
Simplified Block Diagram www.national.com 2 20021731 ...
Page 3
Connection Diagram Order number DS40MB200SQ See NS Package Number SQA48D 3 20021732 www.national.com ...
Page 4
Pin Descriptions Pin Name Pin Number I/O LINE SIDE HIGH SPEED DIFFERENTIAL IO's LI_0 Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an LI_0− 7 internal 50Ω connected to an internal ...
Page 5
Pin Name Pin Number I/O POWER 14, 20 29, 35, 38, Each V 44 via located as close as possible to the landing pad of the recommended to have a ...
Page 6
Functional Description The DS40MB200 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 4.0 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling, see Figure ...
Page 7
TABLE 4. SWITCH-SIDE PRE-EMPHASIS CONTROLS Pre-Emphasis Level in PreS_[1: (VODB 1200 0 1 1200 1 0 1200 1 1 1200 (default) FIGURE 1. Driver Pre-Emphasis Differential Waveform (showing all 4 pre-emphasis steps) De-Emphasis Level Pre-Emphasis in ...
Page 8
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 sec Thermal Resistance, θ JA Thermal Resistance, θ ...
Page 9
Symbol Parameter V Output Pre-Emphasis Voltage Ratio Running K28.7 pattern at 4 Gbps 20*log(VODPE/VODB) PREx_[1:0]=00 PREx_[1:0]=01 PREx_[1:0]=10 PREx_[1:0]=11 x=S for switch side pre-emphasis control x=L for line side pre-emphasis control See Figure 1 on waveform. See Figure ...
Page 10
Symbol Parameter DJ Device Deterministic See Figure 5 for test circuit. Jitter (Notes 6, 8) Pre-emphasis disabled Gbps, PRBS7 pattern DR Maximum Data Rate Tested with alternating-1-0 pattern MAX (Note 8) Note 1: “Absolute Maximum Ratings” are the ...
Page 11
FIGURE 4. Test condition for output pre-emphasis duration FIGURE 5. AC Test Circuit FIGURE 6. Receiver Input Termination and Bias Circuit 11 20021739 20021750 20021734 www.national.com ...
Page 12
Applications Information The DS40MB200 input equalizer provides equalization to compensate about transmission loss from a short backplane transmission line. For characterization purposes, a 25-inch FR4 coupled micro-strip board trace is used in place Finished Trace Trace Length ...
Page 13
FIGURE 8. Data input and output eye patterns with driver set pre-emphasis 13 20021743 www.national.com ...
Page 14
FIGURE 9. System diagram (showing data paths of port 0) www.national.com 14 20021744 ...
Page 15
FIGURE 10. Application diagram (showing data paths of port 0) 15 20021740 www.national.com ...
Page 16
Physical Dimensions www.national.com inches (millimeters) unless otherwise noted LLP-48 Package Order number DS40MB200SQ See NS Package Number SQA48D 16 ...
Page 17
Notes 17 www.national.com ...
Page 18
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...