EVK-DS40MB200 National Semiconductor, EVK-DS40MB200 Datasheet - Page 10

• Manufacturer Part Number: EVK-DS40MB200
• Description: BOARD EVALUATION DS40MB200
• Manufacturer: National Semiconductor

Specifications of EVK-DS40MB200

• Main Purpose: Interface, 2:1 Multiplexer
• Utilized Ic / Part: DS40MB200
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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DJ
DR
Symbol
Note 1: “Absolute Maximum Ratings” are the ratings beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits.
Note 2: Typical parameters measured at V
Note 3: IN+ and IN− are generic names refer to one of the many pairs of complimentary inputs of the DS40MB200. OUT+ and OUT− are generic names refer to
one of the many pairs of the complimentary outputs of the DS40MB200. Differential input voltage V
defined as |OUT+–OUT−|.
Note 4: K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000}
K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010}
Note 5: Device output random jitter is a measurement of the random jitter contribution from the device. It is derived by the equation sqrt(RJ
RJ
Note 6: Device output deterministic jitter is a measurement of the deterministic jitter contribution from the device. It is derived by the equation (DJ
DJ
driving the device.
Note 7: t
between port 0 and port 1. An example is the output skew among data paths from SIA_0± to LO_0±, SIB_0± to LO_0±, SIA_1± to LO_1± and SIB_1± to LO_1
±. Another example is the output skew among data paths from LI_0± to SOA_0±, LI_0± to SOB_0±, LI_1± to SOA_1± and LI_1± to SOB_1±. t
the delay skew of the loopback paths of the same port and between similar data paths between port 0 and port 1. An example is the output skew among data
paths SIA_0± to SOA_0±, SIB_0± to SOB_0±, SIA_1± to SOA_1± and SIB_1± to SOB_1±.
Note 8: Guaranteed by desigh and characterization using statistical analysis.
Timing Diagrams
MAX
OUT
OUT
is the random jitter measured at the output of the device in psrms, RJ
is the peak-to-peak deterministic jitter measured at the output of the device in pspp, DJ
SKO
Device Deterministic
Jitter (Notes 6, 8)
Maximum Data Rate
(Note 8)
is the magnitude difference in the propagation delays among data paths between switch A and switch B of the same port and similar data paths
Parameter
CC
See Figure 5 for test circuit.
Pre-emphasis disabled.
At 4 Gbps, PRBS7 pattern
Tested with alternating-1-0 pattern
= 3.3V, T
FIGURE 3. Propagation Delay from input to output
FIGURE 2. Driver Output Transition Time
A
= 25°C. They are for reference purposes and are not production-tested.
Conditions
IN
10
is the random jitter of the pattern generator driving the device.
IN
is the peak-to-peak deterministic jitter of the pattern generator
ID
is defined as |IN+–IN−|. Differential output voltage V
20021736
Min
4
20021735
(Note 2)
Typ
Max
OUT
30
OUT
SKO
2
– RJ
–DJ
also refers to
IN
2
IN
), where
), where
Units
Gbps
pspp
OD
is