EVK-DS40MB200 National Semiconductor, EVK-DS40MB200 Datasheet - Page 4

• Manufacturer Part Number: EVK-DS40MB200
• Description: BOARD EVALUATION DS40MB200
• Manufacturer: National Semiconductor

Specifications of EVK-DS40MB200

• Main Purpose: Interface, 2:1 Multiplexer
• Utilized Ic / Part: DS40MB200
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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LINE SIDE HIGH SPEED DIFFERENTIAL IO's
LI_0+
LI_0−
LO_0+
LO_0−
LI_1+
LI_1−
LO_1+
LO_1−
SWITCH SIDE HIGH SPEED DIFFERENTIAL IO's
SOA_0+
SOA_0−
SOB_0+
SOB_0−
SIA_0+
SIA_0−
SIB_0+
SIB_0−
SOA_1+
SOA_1−
SOB_1+
SOB_1−
SIA_1+
SIA_1−
SIB_1+
SIB_1−
CONTROL (3.3V LVCMOS)
MUX_S0
MUX_S1
PREL_0
PREL_1
PRES_0
PRES_1
LB0A
LB0B
LB1A
LB1B
RSV
Pin Name
Pin Descriptions
Pin Number
33
34
30
31
10
46
45
40
39
43
42
22
21
28
27
16
15
19
18
37
13
12
36
25
47
48
23
24
26
6
7
9
4
3
1
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Inverting and non-inverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an
internal 50Ω connected to an internal reference voltage. See Figure 6.
Inverting and non-inverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have
an internal 50Ω connected to V
Inverting and non-inverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an
internal 50Ω connected to an internal reference voltage. See Figure 6
Inverting and non-inverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have
an internal 50Ω connected to V
Inverting and non-inverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0
− have an internal 50Ω connected to V
Inverting and non-inverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0
− have an internal 50Ω connected to V
Inverting and non-inverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0
− have an internal 50Ω connected to an internal reference voltage. See Figure 6.
Inverting and non-inverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0
− have an internal 50Ω connected to an internal reference voltage. See Figure 6.
Inverting and non-inverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1
− have an internal 50Ω connected to V
Inverting and non-inverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1
− have an internal 50Ω connected to V
Inverting and non-inverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1
− have an internal 50Ω connected to an internal reference voltage. See Figure 6.
Inverting and non-inverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1
− have an internal 50Ω connected to an internal reference voltage. See Figure 6.
A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state
for mux_0 is switch A.
A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default state
for mux_1 is switch A.
PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±).
PREL_0 and PREL_1 are internally pulled high. See Table 3 for line side pre-emphasis levels.
PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0
±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 4 for switch
side pre-emphasis levels.
A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally
pulled high.
A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally
pulled high.
A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally
pulled high.
A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally
pulled high.
Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND
through an external pull-down resistor.
4
CC
CC
.
.
CC
CC
CC
CC
.
.
.
.
Description