ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet
ADP1828LC-EVALZ
Specifications of ADP1828LC-EVALZ
Related parts for ADP1828LC-EVALZ
ADP1828LC-EVALZ Summary of contents
Page 1
FEATURES Wide bias voltage range 3 Wide power stage input range Wide output voltage range: 0 85% of input voltage o o ±0.85% accuracy ...
Page 2
ADP1828 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Simplified Block Diagram ............................................................... 7 Pin Configurations and Function Descriptions ........................... 8 Typical Performance ...
Page 3
SPECIFICATIONS SYNC = GND, unless otherwise specified. All limits at temperature extremes are guaranteed via corre- EN TRK lation using standard statistical quality control (SQC). T Table 1. ...
Page 4
ADP1828 Parameter OSCILLATOR Oscillator Frequency SYNC Synchronization Range SYNC Input Pulse Width SYNC Pin Capacitance CURRENT SENSE CSL Threshold Voltage CSL Output Current Current Sense Blanking Period GATE DRIVERS DH Rise Time DH Fall Time DL Rise Time DL Fall ...
Page 5
Parameter POWER GOOD FB Overvoltage Threshold FB Overvoltage Hysteresis FB Undervoltage Threshold FB Undervoltage Hysteresis PGOOD Propagation Delay PGOOD Off Leakage Current PGOOD Output Low Voltage 1 Connect IN to VREG when IN < 5.5 V. For applications with IN ...
Page 6
ADP1828 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter IN EN PV, SYNC, FREQ, COMP, SS, FB, PGOOD, CLKSET, CLKOUT, VREG, TRK BST-to-GND, SW-to-GND BST-to-SW BST-to-GND, SW-to-GND transients SW-to-GND negative transients CSL-to-GND DH-to-GND DL-to-PGND PGND-to-GND θ , 20-Lead ...
Page 7
SIMPLIFIED BLOCK DIAGRAM ADP1828 VREG 0.6V REF 0.8V 100kΩ EN CLKOUT CLKOUT DRIVER CLKSET FREQ OSCILLATOR SYNC COMP FB TRK 0.6V SS 90kΩ 6kΩ GND IN LINEAR REG 0.75V 0.55V THERMAL UVLO SHUTDOWN IN LOGIC FAULT CLK PWM RAMP COMPARATOR ...
Page 8
ADP1828 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS FREQ 1 20 SYNC ADP1828 TOP VIEW VREG 5 (Not to Scale) 16 GND 6 15 COMP TRK ...
Page 9
QSOP LSCSP Pin No. Pin No. Mnemonic Description 19 17 CLKSET Clock Set Input. Setting CLKSET to Logic high (connect CLKSET to VREG) sets the CLKOUT to 2× the internal oscillator frequency and is in phase with the oscillator. Setting ...
Page 10
ADP1828 TYPICAL PERFORMANCE CHARACTERISTICS 90 300kHz 600kHz LOAD (A) Figure 5. Efficiency vs. Load Current of Figure 3. ...
Page 11
VREG LOAD CURRENT (mA) Figure 11. VREG vs. Load Current 5.000 4.995 4.990 NO LOAD 4.985 4.980 4.975 10mA LOAD 4.970 ...
Page 12
ADP1828 2 18V 300kHz OR 600kHz 1.5 OSC REFERENCE POINT IS AT 25°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –50 – TEMPERATURE (°C) Figure 17. Δ f vs. ...
Page 13
(AC-COUPLED) 1 OUT 3 CH1 2.00V 4.00ms A CH1 CH3 50.0mV Figure 23. Line Transient Response of Figure 1, No Load SHORT CIRCUIT APPLIED SHORT CIRCUIT REMOVED ...
Page 14
ADP1828 CLKOUT 4 CH2 10.0V M 1.00µs CH3 5.00V CH4 5.00V Figure 29. CLKOUT, CLKSET = CLKOUT CH2 10.0V M 1.00µs CH3 5.00V CH4 5.00V Figure 30. ...
Page 15
THEORY OF OPERATION The ADP1828 is a versatile, synchronous-rectified, fixed- frequency, pulse-width modulation (PWM), voltage mode, step-down controller capable of generating an output voltage as low as 0 85% of the input voltage ideal for a ...
Page 16
ADP1828 If the output voltage is precharged prior to turn-on, the ADP1828 prevents reverse inductor current, which would discharge the output capacitor. Once the voltage at SS exceeds the regulation voltage (typically 0.6 V), the reverse current is re-enabled to ...
Page 17
The PV pin provides power to the low-side drivers limited to 5.5 V maximum input and should have a local decoupling capacitor to PGND. The synchronous rectifier is turned on for a minimum time of about 200 ns ...
Page 18
ADP1828 COMPENSATION The control loop is compensated by an external series RC network from COMP to FB and sometimes requires a series RC in parallel with the top voltage divider resistor. COMP is the output of the internal error amplifier. ...
Page 19
APPLICATION INFORMATION SELECTING THE INPUT CAPACITOR The input current to a buck converter is a pulse waveform zero when the high-side switch is off and approximately equal to the load current when it is on. The input capacitor ...
Page 20
ADP1828 During a load step transient on the output, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. This initial output voltage deviation, due to a change in load, is dependent ...
Page 21
SETTING THE CURRENT LIMIT The current-limit comparator measures the voltage across the low-side MOSFET to determine the load current. The current limit is set through the current-limit resistor, R The current sense pin, CSL, sources 50 μA through the external ...
Page 22
ADP1828 Depending on component selection, one zero might already be generated by the ESR of the output capacitor. Calculate this zero corner frequency ESR ESR 2 π ESR OUT Figure 37 shows ...
Page 23
Use the following guidelines for selecting between Type II and Type III compensators: f ≤ use Type II compensation. f ESRZ 2 f > use Type III compensation ESRZ 2 PHASE CONTRIBUTION AT ...
Page 24
ADP1828 Use the larger value of C from Equation 31 or Equation 32. I Because of the finite output current drive of the error amplifier, C needs to be less than 10 nF larger than 10 nF, ...
Page 25
SOFT START The ADP1828 uses an adjustable soft start to limit the output voltage ramp-up period, limiting the input inrush current. The soft start is selected by setting the capacitor, C GND. The ADP1828 charges C to 0.8 V through ...
Page 26
ADP1828 COMP FB TRK 0.6V ERROR AMPLIFIER SS DETAIL VIEW OF ADP1828 Figure 42. Voltage Tracking COINCIDENT TRACKING The most common application is coincident tracking, used in core vs. I/O voltage sequencing and similar applications. Coincident tracking limits the slave ...
Page 27
A more accurate solution is to provide a divider from the master voltage that sets the TRK pin voltage to be something lower than 0 regulation, for example, 0.5 V. The slave channel can be viewed as having ...
Page 28
ADP1828 THERMAL CONSIDERATIONS The current required to drive the external MOSFETs comprises the vast majority of the power dissipation of the ADP1828. The on-chip LDO regulates down and this 5 V supplies the drivers. The full gate ...
Page 29
PCB LAYOUT GUIDELINE In any switching converter, there are some circuit paths that carry high dI/dt, which can create spikes and noise. Other circuit paths are sensitive to noise. While other circuits carry high dc current and can produce significant ...
Page 30
ADP1828 To achieve an accurate output voltage, proper grounding of the AGND and PGND planes is needed. For light to medium loads, connecting the AGND plane to the PGND plane with a trace is adequate in obtaining good output accuracy ...
Page 31
APPLICATION CIRCUITS C6 R6 1µF 100kΩ R8 8.06kΩ 68pF SS 100nF C3 3.3nF f = 600kHz CERAMIC, 22µF/6.3V/X5R/0805 CERAMIC, 100µF/6.3V/X5R/1210 OUT1 C : CERAMIC, 47µF/6.3V/X5R/1206 OUT2 C7 1µF C6 1µF R6 100kΩ ...
Page 32
ADP1828 BIAS C6 1µF R6 100kΩ R8 4.99kΩ 220pF 100nF C3 4.7nF f = 300kHz SANYO, OSCON 16SP270M SANYO, OSCON 2R5SEPC820M OUT2 L1: COILTRONICS, HC7-1R0 C6 1µF R6 100kΩ ...
Page 33
OUTLINE DIMENSIONS 0.065 (1.65) 0.049 (1.25) 0.010 (0.25) 0.004 (0.10) COPLANARITY 0.004 (0.10) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. PIN 1 INDICATOR ...
Page 34
... ADP1828 ORDERING GUIDE 1 Model Notes Temperature Range ADP1828YRQZ-R7 −40°C to +85°C ADP1828ACPZ-R7 −40°C to +85°C ADP1828LC-EVALZ ADP1828HC-EVALZ 3 ADP1828-BL1-EVZ 3 ADP1828-BL2-EVZ RoHS Compliant Part. 2 Operating junction temperature is –40°C to +125°C. 3 Users can generate schematic design and build of materials from the Analog Devices, Inc., ADIsimPower™, at www.analog.com/ADIsimPower. ...
Page 35
NOTES Rev Page ADP1828 ...
Page 36
ADP1828 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06865-0-11/10(C) Rev Page ...