ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 25

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

SOFT START
The ADP1828 uses an adjustable soft start to limit the output
voltage ramp-up period, limiting the input inrush current. The
soft start is selected by setting the capacitor, C
GND. The ADP1828 charges C
90 kΩ resistor. The voltage on the soft start capacitor while it is
charging is
The soft start period ends when the voltage on the soft start pin
reaches 0.6 V. Substituting 0.6 V for V
start time t
Because R = 90 kΩ:
where t
SWITCHING NOISE AND OVERSHOOT REDUCTION
In any high speed step-down regulator, high frequency noise
(generally in the range of 50 MHz to 100 MHz) and voltage
overshoot are always present at the gate, the switch node (SW),
and the drains of the external MOSFETs. The high frequency
noise and overshoot are caused by the parasitic capacitance,
C
the gate trace and the packages of the MOSFETs. When the
high current is switched, electromagnetic interference (EMI)
is generated, which can affect the operation of the surrounding
circuits. To reduce voltage ringing at the drain of the MOSFET,
an RC snubber can be added between SW and PGND, as illu-
strated in Figure 41. In most applications, R
and C
the following equations:
where:
f is the high frequency ringing measured at the SW node.
C
MOSFETs, given in the MOSFET data sheet.
The size of the RC snubber components need to be chosen
correctly to handle the power dissipation. The power dissipated
in R
gd
OSS
, of the external MOSFET and the parasitic inductance of
SNUB
is the total output capacitance of the top-side and low-side
V
t
C
C
0
R
P
SNUB
SS
6 .
SNUB
CSS
SS
SNUB
SNUB
SS
=
is:
V
=
is the desired soft start time in seconds.
. 1
=
about 1.2 nF. R
t
SS
=
=
=
386
=
0
SS
:
0
V
8 .
C
×
2
8 .
IN
π
OSS
V
8
RC
V
fC
2
μF/
⎛
⎜
⎜
⎝
1
C
⎛
⎜
⎜
⎝
1
SS
OSS
1
SNUB
−
−
sec
e
e
90
f
90
SW
kΩ
SNUB
kΩ
t
t
C
C
SS
SS
and C
⎞
⎟
⎟
⎠
SS
⎞
⎟
⎟
⎠
to 0.8 V through an internal
SNUB
SS
can be calculated using
and solving for the soft
SNUB
SS
, from SS to
is about 2 Ω,
(45)
(46)
(47)
(48)
(49)
(50)
Rev. C | Page 25 of 36
In most applications, a size 0805 component is sufficient. The
use of the RC snubber reduces the overall efficiency, generally
by an amount in the range of 0.1% to 0.5%. However, the RC
snubber cannot reduce the voltage overshoot. A resistor, shown
as R
overshoot and is generally between 1 Ω and 5 Ω.
VOLTAGE TRACKING
The ADP1828 includes a feature that tracks a master voltage.
This feature is especially im
(or other controllers such a
rate power supply voltages, such as the core and I/O voltages of
a DSP or microcontroller. In these cases, improper sequencing
can cause damage to the load.
The ADP1828 tracking input is an additional positive input to
the error amplifier. The feedback voltage is regulated to the lower
of the 0.6 V reference, the SS voltage, or the voltage at TRK, so
a lower voltage on TRK limits the output voltage. This feature
allows implementation of two different types of tracking: coin-
cident tracking, where the output voltage is the same as the
master voltage until the master voltage reaches regulation, or
ratiometric tracking, where the output voltage is limited to a
fraction of the master voltage.
In all tracking configurations, the final value of the master
voltage should be higher than the slave voltage.
Note that the soft start time setting of the master voltage should
be longer than the soft start of the slave voltage. This forces the
rise time of the master voltag
If the soft start setting of the
comes up more slowly and the tr
seen at the output. The slave channe
start capacitor to give a small but reasonable soft start time to
protect the part in case of restart after a current-limit event.
RISE
in Figure 41, at the BST pin could help to reduce
ADP1828
Figure 41. Application Circuit with a Snubber
PV
PGND
BST
CSL
SW
DH
DL
R
RISE
s the ADP1829) are powering sepa-
portant when multiple ADP1828s
slave voltage is longer, the slave
e to be imposed on the slave voltage.
R
CL
acking relationship is not
V
IN
M1
M2
l should still have a soft
R
C
SNUB
SNUB
L
V
ADP1828
OUT
C
OUT