ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 29

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

PCB LAYOUT GUIDELINE
In any switching converter, there are some circuit paths that
carry high dI/dt, which can create spikes and noise. Other
circuit paths are sensitive to noise. While other circuits carry
high dc current and can produce significant IR voltage drops.
The key to proper PCB layout of a switching converter is to
identify these critical paths and arrange the components and
the copper area accordingly. When designing PCB layouts,
be sure to keep high current loops small. In addition, keep
compensation and feedback components away from the switch
nodes and their associated components.
The following is a list of recommended layout practices for the
synchronous buck controller arranged by decreasing order of
importance:
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•
•
The current waveform in the top and bottom FETs is a
pulse with very high dI/dt, so the path to, through, and
from each individual FET should be as short as possible
and the two paths should be commoned as much as possible.
In designs that use a pair of D-Pak or a pair of SO-8 FETs
on one side of the PCB, it is best to counter-rotate the two
so that the switch node is on one side of the pair and the
high-side drain can be bypassed to the low-side source
with a suitable ceramic bypass capacitor, placed as close
as possible to the FETs in order to minimize inductance
around this loop through the FETs and capacitor. The recom-
mended bypass ceramic capacitor values range from 1 μF to
22 μF depending upon the output current. This bypass
capacitor is usually connected to a larger value bulk filter
capacitor and should be grounded to the PGND plane.
The negative terminals of GND, IN bypass, and a soft start
capacitor (as well as the bottom end of the output feedback
divider resistors) should be tied to an almost isolated small
AGND plane. All of these connections should attach from
their respective pins to the AGND plane that are as short as
possible. No high current or high dI/dt signals should be
connected to this AGND plane. The AGND area should be
connected through one wide trace to the negative terminal
of the output filter capacitors.
The PGND pin handles a high dI/dt gate drive current
returning from the source of the low-side MOSFET. The
voltage at this pin also establishes the 0 V reference for
the overcurrent limit protection function and the CSL
pin. A PGND plane should connect the PGND pin and the
PV bypass capacitor, 1 μF, through a wide and direct path
to the source of the low-side MOSFET. The placement of
C
terminal of C
of the low-side MOSFET.
IN
is critical for controlling ground bounce. The negative
IN
needs to be placed very close to the source
Rev. C | Page 29 of 36
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Avoid long traces or large copper areas at the FB and CSL
pins, which are low signal level inputs that are sensitive to
capacitive and inductive noise pickup. It is best to position
any series resistors and capacitors as closely as possible to
these pins. Avoid running these traces close and/or parallel
to high dI/dt traces.
The switch node is the noisiest place in the switcher
circuit with large ac and dc voltages and currents. This
node should be wide to keep resistive voltage drop down.
But, to minimize the generation of capacitively coupled
noise, the total area should be small. Place the FETs and
inductor close together on a small copper plane in order to
minimize series resistance and keep the copper area small.
Gate drive traces (DH and DL) handle high dI/dt and tend
to produce noise and ringing. They should be as short and
direct as possible. If possible, avoid using feedthrough vias
in the gate drive traces. If vias are needed, it is best to use
two relatively large ones in parallel to reduce the peak
current density and the current in each via. If the overall
PCB layout is less than optimal, slowing down the gate
drive slightly can be very helpful to reduce noise and
ringing. It is occasionally helpful to place small value
resistors (such as 5 Ω or10 Ω) in between the DH and
DL pins and their respective MOSFET gates. These can
be populated with 0 Ω resistors if resistance is not needed.
Note that the added gate resistance increases the switching
rise and fall times as well as switching power loss in the
MOSFET.
The negative terminal of the output filter capacitors
should be tied closely to the source of the low-side FET.
Doing this helps to minimize voltage differences between
GND and PGND.
All traces should be sized according to the current that is
handled as well as their sensitivity in the circuit. Standard
PCB layout guidelines mainly address the heating effects of
a current in a copper conductor. While these are completely
valid, they do not fully cover other concerns such as stray
inductance or dc voltage drop. Any dc voltage differential
in connections between ADP1828 GND and the converter
power output ground can cause a significant output voltage
error, as it affects converter output voltage according to the
ratio with the 600 mV feedback reference. For example, a
6 mV offset between ground on the ADP1828 and the
converter power output causes a 1% error in the converter
output voltage.
ADP1828