ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 21

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

SETTING THE CURRENT LIMIT
The current-limit comparator measures the voltage across the
low-side MOSFET to determine the load current.
The current limit is set through the current-limit resistor, R
The current sense pin, CSL, sources 50 μA through the external
current-limit setting resistor, R
of R
across the low-side MOSFET R
this offset voltage, the ADP1828 flags a current-limit event.
Because the CSL current and the MOSFET R
process and temperature, the minimum current limit should be
set to ensure that the system can handle the maximum desired
load current. To do this, use the peak current in the inductor,
which is the desired current-limit level plus the ripple current,
the maximum R
temperature, and the minimum CSL current:
where:
I
−38 mV is the CSL threshold voltage.
Because the buck converters are usually running a fairly high
current, PCB layout and component placement may affect the
current-limit setting. An iteration of the R
for a particular board layout and MOSFET selection. If alternate
MOSFETs are substituted at some point in production, these
resistor values may also need an iteration.
ACCURATE CURRENT-LIMIT SENSING
The R
than 50% over the temperature range. Accurate current-limit
sensing can be achieved by adding a current sense resistor from
the source of the low-side MOSFET to PGND. Make sure that
the power rating of the current sense resistor is adequate for
the application. Apply Equation 14 to calculate R
R
FEEDBACK VOLTAGE DIVIDER
The output regulation voltage is set through the feedback volt-
age divider. The output voltage is divided down through the
voltage divider and drives the FB feedback input. The regulation
threshold at FB is 0.6 V. The maximum input bias current into
LPK
DSON(MAX)
is the peak inductor current.
CL
R
DSON
multiplied by the 50 μA CSL current. When the drop
CL
=
with R
of the external low-side MOSFET can vary by more
I
LPK
ADP1828
Figure 36. Accurate Current-Limit Sensing
DSON
R
SENSE
DSON
CSL
DH
DL
of the MOSFET at its highest expected
.
42
(
MAX
μ
A
R
)
CL
−
V
38
IN
CL
DSON
R
. This creates an offset voltage
mV
M1
M2
SENSE
is equal to or greater than
L
CL
V
OUT
value may be required
C
DSON
OUT
CL
vary over
and replace
CL
(14)
Rev. C | Page 21 of 36
.
FB is 100 nA. For a 0.15% degradation in regulation voltage and
with 100 nA bias current, the low-side resistor, R
less than 9 kΩ, which results in 67 μA of divider current. For
R
used, but results in a reduction in output voltage accuracy due
to the input bias current at the FB pin, while lower values cause
increased quiescent current consumption. Choose R
the output voltage by using the following equation:
where:
R
R
V
V
COMPENSATING THE VOLTAGE MODE BUCK
REGULATOR
Assuming the LC filter design is complete, the feedback control
system can then be compensated. Good compensation is critical
to proper operation of the regulator. Calculate the quantities in
Equation 16 through Equation 44 to derive the compensation
values. The goal is to guarantee that the voltage gain of the buck
converter crosses unity at a slope that provides adequate phase
margin for stable operation. Additionally, at frequencies above
the crossover frequency (f
and attenuation of switching noise are important secondary
goals. For initial practical designs, a good choice for the
crossover frequency is one tenth of the switching frequency,
calculate first
This gives sufficient frequency range to design a compensation
scheme that attenuates switching artifacts, while also giving
sufficient control loop bandwidth to provide a good transient
response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a frequency (f
Generally speaking, the LC corner frequency is about two
orders of magnitude below the switching frequency, and
therefore about one order of magnitude below crossover.
To achieve sufficient phase margin at crossover to guarantee
stability, the design must compensate for the two poles at the
LC corner frequency with two zeros to boost the system phase
prior to crossover. The two zeros require an additional pole or
two above the crossover frequency to guarantee adequate gain
margin and attenuation of switching noise at high frequencies.
BOT
TOP
BOT
OUT
FB
is the feedback regulation threshold, 0.6 V.
, use a 1 kΩ to 10 kΩ resistor. A larger value resistor can be
is the high-side voltage divider resistance.
is the low-side voltage divider resistance.
is the regulated output voltage.
R
f
f
CO
LC
TOP
=
=
=
2
f
10
π
SW
R
1
BOT
LC
⎛
⎜
⎜
⎝
V
OUT
V
CO
−
FB
), guaranteeing sufficient gain margin
V
FB
⎞
⎟
⎟
⎠
LC
). Next, calculate
BOT
ADP1828
, needs to be
TOP
to set
(15)
(16)
(17)