ADP1828LC-EVALZ Analog Devices Inc, ADP1828LC-EVALZ Datasheet - Page 15

• Manufacturer Part Number: ADP1828LC-EVALZ
• Description: BOARD EVALUATION ADP1828LC
• Manufacturer: Analog Devices Inc

Specifications of ADP1828LC-EVALZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 5A
• Voltage - Input: 5.5 ~ 13.2V
• Regulator Topology: Buck
• Frequency - Switching: 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ADP1828
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

THEORY OF OPERATION
The ADP1828 is a versatile, synchronous-rectified, fixed-
frequency, pulse-width modulation (PWM), voltage mode,
step-down controller capable of generating an output voltage
as low as 0.6 V to 85% of the input voltage. It is ideal for a wide
range of applications, such as DSP and processor core I/O supplies,
general-purpose power in telecom, medical imaging, gaming,
PCs, set-top boxes, and industrial controls. The ADP1828
controller operates directly from 3 V to 20 V. It includes fully
integrated MOSFET gate drivers and a linear regulator for
internal and gate drive bias.
The ADP1828 operates at a pin-selectable, fixed switching
frequency of either 300 kHz or 600 kHz, or operates at any
frequency between 300 kHz and 600 kHz by connecting a
resistor between FREQ and GND. The switching frequency
can also be synchronized to an external clock up to 2× the
part’s nominal oscillator frequency. The built-in clock output
can be used for synchronizing the ADP1829 and other ADP1828
controllers, thus eliminating the need for an external clock
source. The ADP1828 also includes clockout, voltage tracking,
thermal overload protection, undervoltage lockout, power
good, soft start to limit inrush current from the input supply
during startup, reverse current protection during soft start for
precharged outputs, and an adjustable lossless current-limit
scheme utilizing external MOSFET R
operates over the −40°C to +125°C junction temperature range
and is available in a 20-lead QSOP.
INPUT POWER
The ADP1828 is powered from the IN pin from 3.0 V up to
20 V. The internal low dropout linear regulator, regulates the
IN voltage down to 5 V when IN is between 5.5 V and 20 V.
The output of the LDO is denoted as VREG. The control circuits,
gate drivers, and the external boost capacitor operate from the
LDO output for IN between 5.5 V and 20 V. PV powers the
low-side MOSFET gate drive (DL), and IN powers the internal
control circuitry. Bypass PV to PGND with a 1 μF or greater
capacitor, and bypass IN to GND with a 0.1 μF or greater
capacitor. Bypass the power input to PGND with a suitably
large capacitor.
The VREG output is sensed by the undervoltage lock-out
(UVLO) circuit to be certain that enough voltage headroom
is available to run the controllers and gate drivers. As VREG
rises above about 2.7 V, the controllers are enabled. The IN
voltage is not directly monitored by the UVLO circuit. If the
IN voltage is insufficient to allow VREG to be above the
UVLO threshold, the controllers are disabled, but the LDO
continues to operate. The LDO is enabled and cannot be
turned off whenever EN is high, even if VREG is below the
UVLO threshold.
DSON
sensing. The ADP1828
Rev. C | Page 15 of 36
For a supply voltage between 5.5 V and 20 V, connect IN to the
supply voltage, and tie VREG to PV. For a supply voltage between
3 V and 5.5 V, connect IN, PV, and VREG to the supply voltage.
In this case, the input supply voltage directly powers the low-
side gate driver.
While IN is limited to 20 V, the switching stage can run from
up to 24 V and the BST pin can go to 30 V to support the gate
drive. This can provide an advantage, for example, in the case
of high frequency operation from high input voltage. Power
dissipation in the ADP1828 can be limited by running IN from
a low voltage rail while operating the switches from the high
voltage rail.
INTERNAL LINEAR REGULATOR
The internal linear regulator has low dropout, meaning it can
regulate its output voltage (VREG) close to the input voltage.
It powers up the internal control circuitry and provides bias
for the gate drivers when VREG is tied to PV. It is guaranteed
to have more than 100 mA of output current capability, which
is sufficient to handle the gate drive requirements of typical
logic threshold MOSFETs driven at up to 1.2 MHz. Bypass
VREG to AGND with a 1 μF or greater capacitor.
Because the LDO supplies the gate drive current, the output
of VREG is subjected to sharp transient currents as the drivers
switch and the boost capacitors recharge during each switching
cycle. The LDO has been optimized to handle these transients
without overload faults. Due to the gate drive loading, using
the VREG output for other auxiliary system loads is not
recommended.
The LDO includes a current limit well above the expected
maximum gate drive load. This current limit also includes a
short-circuit fold back to further limit the VREG current in
the event of a short-circuit fault.
SOFT START
The ADP1828 employs a programmable soft start that reduces
input current transients and prevents output overshoot. SS drives
an auxiliary positive input to the error amplifier; thus, the voltage
at this pin regulates the voltage at the feedback control pin.
Program the soft start by connecting a capacitor from SS to
GND. On startup, the capacitor charges from an internal
90 kΩ resistor to 0.8 V. The dc-to-dc converter output voltage
rises with the voltage at the soft start pin, allowing the output
voltage to rise slowly and reducing the inrush current.
ADP1828