ISL8105BEVAL1Z Intersil, ISL8105BEVAL1Z Datasheet
ISL8105BEVAL1Z
Specifications of ISL8105BEVAL1Z
Related parts for ISL8105BEVAL1Z
ISL8105BEVAL1Z Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 All other trademarks mentioned are the property of their respective owners. ISL8105B April 15, 2010 FN6447.2 Output Voltage Range IN (+5V to +12V) DS(ON) | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2010. All Rights Reserved ...
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... NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...
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Block Diagram SAMPLE AND HOLD 21.5µA TO BGATE/BSOC FB 5V INT. 0.4V 20µA COMP/EN POR AND SOFT-START + - OC COMPARATOR 5V INT. PWM COMPARATOR 0. ERROR AMP DIS + - OSCILLATOR FIXED 300kHz VBIAS D ...
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... Package +150°C BOOT . . . . . . . . . . . . . . . .15V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Bias Voltage, V Ambient Temperature Range ISL8105BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL8105BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Junction Temperature Range .-40°C to +125°C ...
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Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYMBOL TGATE Sink Resistance R BGATE ...
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MOSFET has turned off. N/C (DFN Only; Pin3, Pin 7) These two pins in the DFN package are Not Connected. Functional Description Initialization (POR and OCP Sampling) Figure 1 shows a start-up waveform of ...
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V OVER-CHARGED OUT V PRE-BIASED OUT V NORMAL OUT t0 t1 FIGURE 3. SOFT-START WITH PRE-BIAS soft-start ramp voltage exceeds the output; V seamlessly ramping from there. If the output is pre-biased to a voltage above the expected value, as ...
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BGATE > 425ns BGATE > 425ns BGATE = 425ns BGATE = 425ns BGATE < 425ns BGATE < 425ns BGATE < 425ns BGATE << 425ns FIGURE 4. BGATE PULSE STRETCHING The overcurrent function will trip at a peak inductor current (I ...
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V OUT 2 SOFT-START CYCLES t0 t1 FIGURE 5. OVERCURRENT RETRY OPERATION Output Voltage Selection The output voltage can be programmed to any level between the 0.6V internal reference the V ISL8105B can run at near 100% duty ...
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Another consideration for high V is duty cycle. Very low IN duty cycles (such as 20V in to 1.0V out, for 5% duty cycle) require component selection compatible with that choice (such as low r bottom-side MOSFET, and a good ...
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Locate the capacitor close as practical to BOOT the BOOT and LX pins. All components used for feedback compensation (not shown) should be located as close to the IC as practical. Feedback Compensation This section highlights ...
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ESR C 1 MAX ⋅ G ----------------------------- - ---------------------------------------------------------------------------------------------------------- - = MOD ⋅ ( OSC 1 ESR + ...
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One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8105B will provide either 0% or 100% duty cycle in response ...
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... The resulting higher V G-S gain in efficiency should be balanced against the extra cost and area of the external diode. For information on the Application circuit, including a complete Bill-of-Materials and circuit board description, can be found in Application Note AN1288. http://www.intersil.com/data/an/AN1288.pdf less BIAS , 2 +V BIAS +1V TO +12V ...
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... Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2 TERMINAL TIP MILLIMETERS MIN ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...