ISL6740EVAL2Z Intersil, ISL6740EVAL2Z Datasheet
ISL6740EVAL2Z
Specifications of ISL6740EVAL2Z
Related parts for ISL6740EVAL2Z
ISL6740EVAL2Z Summary of contents
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... All other trademarks mentioned are the property of their respective owners. ISL6740, ISL6741 July 13, 2007 FN9111.4 ISL6740, ISL6741 (16 LD SOIC TSSOP) TOP VIEW OUTA 1 16 OUTB GND REF SCSET SYNC OTS FAULT ERROR Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved ...
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Functional Block Diagram VDD VREF VREF 5. ENABLE + - GND N_SYNC OUT INTERNAL OT SHUTDOWN BI-DIRECTIONAL +130°C TO +150°C SYNCHRONIZATION SYNC IN INHIBIT/VIN UV 1.00V + EXT. SYNC INHIBIT UV - IRTC OSCILLATOR RTC ...
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Functional Block Diagram (Continued) VREF VDD VREF 5. ENABLE + - + - BG GND N_SYNC OUT INTERNAL OT SHUTDOWN BI-DIRECTIONAL +130°C TO +150°C SYNCHRONIZATION INHIBIT/VIN UV 1. EXT. SYNC INHIBIT UV - IRTC OSCILLATOR RTC ...
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Typical Application (ISL6740) - 48V Input DC Transformer, 12V @ 8A Output (ISL6740EVAL1) VIN CR3 VIN- R7 TP6 C13 R10 TP1 T2 QL C14 R11 CR2 CR1 R5 ...
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... Typical Application (ISL6740) - 36V to 75V Input, Regulated 12V @ 8A Output (ISL6740EVAL2Z) VIN CR3 36V TO 75V VIN- R7 TP6 Q5 D1 R26 CR5 C13 R10 TP1 T2 CR6 R27 QL C14 R11 CR2 CR1 R14 R5 U1 TP4 HIP2101 VDD LO HB VSS RT1 TP5 U3 GND VERROR OUTB CS OUTA ...
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Typical Application (ISL6741) - 48V to 5V Push-Pull DC/DC Converter +48V C1 Q1 SYNC R2 R1 VIN VR1 + 5V QR1 R18 T1 EL7242 QR2 U5 RT1 Q2 R12 R11 R3 GND VERROR OUTB CS ...
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... ISL6740, 1SL6741 Thermal Information Thermal Resistance Junction to Ambient (Typical) 16 Lead SOIC (Note REF 16 Lead TSSOP (Note Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp < 51.1kΩ 10kΩ +25°C A ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. 9V < V values are at T PARAMETER PULSE WIDTH MODULATOR V Input Impedance ERROR Minimum Duty Cycle Maximum Duty Cycle V to PWM ...
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Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application Schematic. 9V < V values are at T PARAMETER Overcurrent/Short Circuit Discharge Current Fault SS Discharge Current Reset Threshold Voltage FAULT Fault High Level Output ...
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Typical Performance Curves 1.001 1.000 0.999 0.998 0.997 -40 -25 - TEMPERATURE (°C) FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE 4 1•10 CT (pF) = 1000 680 470 330 3 1•10 220 100 100 ...
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The ISL6740, ISL6741 features a built-in soft-start. Soft-start is implemented as a clamp on the error voltage input. OTS - The non-inverting input to the over-temperature shutdown comparator. ...
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Oscillator The ISL6740, ISL6741 have an oscillator with a programmable frequency range to 2MHz, which can be programmed with two resistors and capacitor. The use of three timing elements and flexibility and precision ...
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The voltage hysteresis created by the switched current source and the external impedance is generally small due to the large resistor divider ratio required to scale the input voltage down to the UV threshold level. A small capacitor placed between ...
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Fault Conditions A fault condition occurs if V falls below 4.65V, the UV REF input falls below 1.00V, the thermal protection is triggered OTS faults. When a fault is detected, OUTA and OUTB outputs are disabled, the Fault ...
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Circuit Element Descriptions The converter design may be broken down into the following functional blocks: Input Filtering Half-Bridge Capacitors Isolation Transformer Primary Snubber ...
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The TDK datasheet for PC44 material indicates a core loss factor of 3 ~400mW/cm with a ±2000 gauss 100kHz sinusoidal excitation. The application uses a ...
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The order and geometry of the windings affects the AC resistance, winding capacitance, and leakage inductance of the finished transformer. To mitigate these effects, interleaving the windings is necessary. The primary winding is sandwiched between the two secondary windings. The ...
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MOSFET Selection The criteria for selection of the primary side half-bridge FETs and the secondary side synchronous rectifier FETs is largely based on the current and voltage rating of the device. However, the FET drain-source capacitance and gate charge cannot ...
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A value of 220pF was selected. To obtain the proper value for R , Equation 3 is used. TD Since there is a 10ns propagation delay in the oscillator circuit, it must be included in the ...
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The divider between RTC and GND formed by R13 and R15 determines the percent of maximum duty cycle that corresponds to a short circuit. The divider ratio formed by R13 and R15 is R15 1.27k ---------------------------- ...
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... FET, Fairchild FDS5670 Resistor, 2512, 5% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 0805, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, Open Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Midcom 31718 Pulse P8205T Intersil HIP2101IB ISL6740IB FN9111.4 July 13, 2007 ...
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... Adding Regulation - Closed Loop Feedback 100k The second Typical Application schematic adds closed loop feedback with isolation. The ISL6740EVAL2Z demonstration platform implements this design and is available for evaluation. The input voltage range was increased to 36V to 75V, which necessitates a few modifications to the open loop design. The output inductor value was increased to 4.0μ ...
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A block diagram of the feedback control loop follows in Figure 19. POWER PWM STAGE ERROR AMPLIFIER Z 2 ISOLATION FIGURE 19. CONTROL LOOP BLOCK DIAGRAM The loop compensation is placed around the Error Amplifier (EA) on the secondary side ...
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The higher the desired bandwidth of the converter, the more difficult create a solution that is stable over the entire operating range. A good rule of thumb is to limit the bandwidth to about f /4, where ...
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The gain and phase plots combined with the opto coupler’s transfer characteristics appear in Figures 24A and 24B - 100 1•10 1•10 FREQUENCY (Hz) FIGURE 24A. EA PLUS OPTO COUPLER GAIN ...
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... The actual loop gain and phase margin measured on the ISL6740EVAL2Z demonstration board appear in Figures 26A and 26B -10 -20 -30 -40 -50 0.1k 1k FREQUENCY (Hz) FIGURE 26A. MEASURED LOOP GAIN 225 180 135 -45 -90 -135 0.1k 1k FREQUENCY (Hz) FIGURE 26B. MEASURE LOOP PHASE MARGIN The only major discrepancies between the predicted behavior and the measured results are the Q of the L-C filter and the phase behavior above 60kHz ...
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... Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, Open Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 0603, 1% Midcom 31660-LF1 Pulse P8205NL Intersil HIP2101IBZ NEC PS2801-1-A ISL6740IBZ National LM431BIM3/NOPB FN9111.4 July 13, 2007 ...
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Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - -C- α 0.10(0.004) 0.10(0.004 NOTES: 1. These package ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...