ISL6269AEVAL2Z Intersil, ISL6269AEVAL2Z Datasheet - Page 12

• Manufacturer Part Number: ISL6269AEVAL2Z
• Description: EVALUATION BOARD FOR ISL6269A
• Manufacturer: Intersil
• Series: Robust Ripple Regulator™ (R³)r

Specifications of ISL6269AEVAL2Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.1V or 1.2V
• Current - Output: 5A
• Voltage - Input: 5 ~ 25V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz or 600kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6269A, ISL6269B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn off, the high-side MOSFET turns off with
V
emphasizes low r
conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as:
For the high-side MOSFET, (HS), its conduction loss is
written as:
For the high-side MOSFET, its switching loss is written as:
Where:
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor is written as:
Where:
As an example, suppose the high-side MOSFET has a total
gate charge Q
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin select a capacitor that is double the
calculated capacitance, in this example 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the compensation
P
P
P
C
IN
CON_LS
CON_HS
SW_HS
- I
- I
- t
- t
BOOT
- Q
- ΔV
- V
inductor current minus 1/2 of the inductor ripple current
current plus 1/2 of the inductor ripple current
saturation
high-side MOSFET
the boot capacitor each time the high-side MOSFET is
switched on
VALLEY
PEAK
ON
OFF
g
OUT
BOOT
is the total gate charge required to turn on the
=
is the time required to drive the device into
=
≈
is the time required to drive the device into cut-off
=
----------------------- -
ΔV
- V
is the sum of the DC component of the inductor
I
V
---------------------------------------------------------------- -
LOAD
I
, is the maximum allowed voltage decay across
IN
LOAD
is the difference of the DC component of the
L
Q
BOOT
g
across it. The preferred low-side MOSFET
•
g
, of 25nC at V
I
VALLEY
2
DS(ON)
2
r ⋅
•
DS ON
r
DS ON
2
(
(
•
when fully saturated to minimize
t
ON
)_LS
)_HS
12
•
GS
f
SW
•
(
•
= 5V, and a ΔV
1 D
D
+
–
V
------------------------------------------------------------ -
IN
)
•
I
PEAK
2
•
t
OFF
BOOT
•
(EQ. 18)
(EQ. 16)
(EQ. 17)
(EQ. 19)
f
SW
of
ISL6269A
components, and the FSET components. The island should be
connected to the rest of the ground plane layer at one point.
Signal Ground and Power Ground
The bottom of the ISL6269A QFN package is the signal
ground (GND) terminal for analog and logic signals of the IC.
Connect the GND pad of the ISL6269A to the island of
ground plane under the top layer using several vias, for a
robust thermal and electrical conduction path. Connect the
input capacitors, the output capacitors, and the source of the
lower MOSFETs to the power ground plane.
PGND (Pin 10)
This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
the source of the low-side MOSFET with a low-resistance,
low-inductance path .
VIN (Pin 1)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
VCC (Pin 2)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 12)
For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269A IC.
FCCM (Pin 3), EN (Pin 4), and PGOOD (Pin 16)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
COMP (Pin 5), FB (Pin 6), and VO (Pin 8)
For best results, use an isolated sense line from the output
load to the VO pin. The input impedance of the FB pin is
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND
pins keeping the high impedance trace short.
FSET (Pin 7)
This pin requires a quiet environment. The resistor R
and capacitor C
this pin. Keep fast moving nodes away from this pin.
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
HIGH-SIDE
MOSFETS
GROUND
VIAS TO
PLANE
FSET
should be placed directly adjacent to
PHASE
NODE
VOUT
GND
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
May 30, 2007
FSET
FN9253.2