HIP6021EVAL1 Intersil, HIP6021EVAL1 Datasheet - Page 12

• Manufacturer Part Number: HIP6021EVAL1
• Description: EVALUATION BOARD HIP6021
• Manufacturer: Intersil

Specifications of HIP6021EVAL1

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Voltage - Output: 1.3 ~ 3.5V, 1.5V, 1.8V, 1.5V or 3.3V
• Current - Output: 10A, 1A, 1A, 1A
• Voltage - Input: 3.3V, 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 200kHz
• Board Type: Fully Populated
• Utilized Ic / Part: HIP6021
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

+5V
+3.3V
V
FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND
V
FIGURE 9. VOLTAGE-MODE BUCK CONVERTER
+3.3V
OUT3
IN
OUT2
∆
V
IN
OSC
IN
C
L
C
C
OUT3
OSC
IN
OUT2
IN
ISLANDS
COMPENSATION DESIGN
Q3
C
ERROR
AMP
Q4
DETAILED COMPENSATION COMPONENTS
V
HIP6021
SS
E/A
COMP
PWM
+12V
Z
+
KEY
-
COMP
FB
-
+
SS
C1
DRIVE2
DRIVE3
REFERENCE
VCC
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
C2
C
HIP6021
DACOUT
+
-
VCC
PGND
R2
12
OCSET1
UGATE1
PHASE1
DRIVER
DRIVER
LGATE1
GND
DRIVE4
Z
IN
FB
Z
V
FB
C
Q2
IN
OCSET1
PHASE
(PARASITIC)
Q5
C3
L
Z
R1
Q1
O
IN
R
L
C
CR1
C
OUT1
OCSET1
OUT4
R3
ESR
OUT1
C
O
V
OUT
V
OUT4
V
V
OUT1
OUT
HIP6021
Compensation Break Frequency Equations
Figure 10 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown in Figure 9. Using the
above guidelines should yield a Compensation Gain similar
to the curve plotted. The open loop error amplifier gain
bounds the compensation gain. Check the compensation
gain at F
Closed Loop Gain is constructed on the log-log graph of
Figure 10 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
F
F
FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
-----------------------------------
2π R
------------------------------------------------------ -
2π
10
MODULATOR
20
P2
×
×
IN
log
GAIN
(
with the capabilities of the error amplifier. The
R1
1
to provide a stable, high bandwidth (BW) overall
2


R2
------- -
R1
100
×
F
+
1
C1
Z1


R3
)
F
×
1K
LC
C3
F
FREQUENCY (Hz)
Z2
F
ESR
10K
F
F
F
P1
P2
P1
=
=
100K
F
------------------------------------------------------ -
2π
-----------------------------------
2π
P2
×
×
R
R
1
1M
2
3
×
ERROR AMP GAIN
×
1
COMPENSATION


C3
C1
--------------------- -
C1
OPEN LOOP
CLOSED LOOP
20
10M
log
×
+
GAIN
C2
C2



GAIN
----------- -
V
V


PP
IN


