MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 107

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.23.1
Table 73
memory bus.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in synchronous mode, the
memory bus is clocked relative to the platform clock frequency. When running in asynchronous mode, the memory bus is
clocked with its own dedicated PLL.
DDR Memory bus clock speed
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. The Memory bus clock refers to the MPC8536E memory controllers’ MCK[0:5] and MCK[0:5] output clocks, running at half of
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. See
Freescale Semiconductor
CCB frequency
DDR Data Rate
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
e500 core processor
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See
Section 2.23.4, “DDR/DDRCLK PLL Ratio,”
the DDR data rate.
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
Ratio.”
data rate.
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to
“DDR/DDRCLK PLL
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically
possible via valid clock ratio setting in some condition, is not supported.
Characteristic
frequency
provides the clocking specifications for the processor cores and
Characteristic
The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR
Clock Ranges
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Min
600
400
Ratio,” for ratio settings.
400
Section 2.23.2, “CCB/SYSCLK PLL
600 MHz
Section 2.23.2, “CCB/SYSCLK PLL
Max
600
400
400
Table 73. Processor Core Clocking Specifications
Table 74. Memory Bus Clocking Specifications
Table 74
Min
600
400
400
800 MHz
Maximum Processor Core Frequency
600, 800, 1000, 1250,1333, 1500MHz
Max
800
400
400
Maximum Processor Core Frequency
Min
200
for ratio settings.
provides the clocking specifications for the memory bus.
Min
600
333
400
1000 MHz
1000
Max
400
400
Ratio” and
Ratio,”
Min
600
333
400
1250 MHz
Section 2.23.3, “e500 Core PLL Ratio“, Section 2.23.4,
Max
333
1250
Max
Section 2.23.3, “e500 Core PLL
Table 74
500
500
Min
600
333
400
1333 MHZ
provides the clocking specifications for the
Section 2.23.4, “DDR/DDRCLK PLL
1333
Max
533
667
MHz
Unit
Min
600
333
400
1500 MHz
1500
Max
500
667
Ratio,” and
MHz
Unit
1, 2, 3, 4
Notes
Clocking
Notes
1, 2
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