MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 29

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4
2.4.1
Table 6
2.4.2
When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK
input, but instead the PCI_CLK.
At recommended operating conditions (see
2.4.3
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the
counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC
signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2 × t
low time is 2 × t
Freescale Semiconductor
At recommended operating conditions (see
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow
4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies. See
settings.
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
SYSCLK.
PCICLK frequency
PCICLK cycle time
PCICLK rise and fall time
PCICLK duty cycle
Notes:
1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.
provides the system clock (SYSCLK) AC timing specifications for the MPC8536E.
Input Clocks
Parameter/Condition
System Clock Timing
PCI Clock Timing
Real Time Clock Timing
Parameter/Condition
CCB
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
. There is no minimum RTC frequency; RTC may be grounded if not needed.
Section 2.23.2, “CCB/SYSCLK PLL Ratio,”
Table 7
Table 6. SYSCLK AC Timing Specifications
Table 7. PCICLK AC Timing Specifications
Table
provides the PCI reference clock AC timing specifications for the MPC8536E.
Table
2) with OV
2) with OV
t
KHK
t
KHK
Symbol
f
t
t
Symbol
SYSCLK
SYSCLK
f
t
t
KH
PCICLK
PCICLK
KH
DD
/t
/t
—
SYSCLK
, t
, t
PCICLK
= 3.3 V ± 165 mV
KL
KL
DD
= 3.3 V ± 165 mV
Min
0.6
Min
33
15
40
7.5
0.6
33
40
—
and
.
Section 2.23.3, “e500 Core PLL Ratio,”
Typical
.
Typical
1.0
—
—
—
1.0
—
—
—
—
Max
2.1
+/-150
66
30
60
Max
133
2.1
30
60
CCB
MHz
Unit
ns
ns
, and minimum clock
%
MHz
Unit
ns
ns
ps
%
Input Clocks
Notes
—
—
—
1
Notes
for ratio
3, 4
—
—
1
2
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