MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 55

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference
clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
2.9.3.1
The characteristics and DC requirements of the separate SerDes reference clock are described in
Serial Interfaces.”
2.9.3.2
Table 38
not intended to be used with, and should not be clocked by, a spread spectrum clock source.
Notes:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12.
3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps.
Freescale Semiconductor
Symbol
t
t
REFCJ
REFPJ
t
REF
lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent
REFCLK cycles
Phase jitter. Deviation in edge location with respect to mean edge location
DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3
Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Parameter Description
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Min
–50
—
—
Typical
10 (8)
Section 2.20, “High-Speed
—
—
Max
100
50
—
Units Notes
ns
ps
ps
2,3
—
1
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