HW-V5-ML525-UNI-G Xilinx Inc, HW-V5-ML525-UNI-G Datasheet - Page 2

• Manufacturer Part Number: HW-V5-ML525-UNI-G
• Description: EVAL PLATFORM ROCKET IO VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML525-UNI-G

• Contents: ML52x Platform, Power Supply, Cables and Documentation
• For Use With/related Products: Virtex™-5 LXT
• For Use With: HW-XGI-SCLK-G - MODULE SUPER CLOCKHW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-NQSL-G - NQSL NELCO QUAD SERIAL LOOPHW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-SDRAM - EXPANSION MOD SDRAM BERG-SDRAM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Revision History
The following table shows the revision history for this document.
ML52x User Guide
03/02/07
08/06/07
04/17/08
08/04/10
Date
Version
1.0
1.1
2.0
2.1
Initial Xilinx release.
Removed UG091, Xilinx Generic Interface (XGI) SuperClock Module User Guide
from“Package Contents.”
Added Power Supply Block Diagram,
“18. DDR2 Memory,” page
connections for A11 and A12 in
Table 15
Added GTX transceiver and FXT device information. Updated VCCINT for ML525 in
Table
Added Voltage Adjust Potentiometer column in
“3. FPGA Configuration.”
Micron part numbers in
Corrected CTS and RXD pins in
designators in
Renumbered XGI pins in columns E and F and corrected XGI pin F27 description in
Table
Table
Section
connectors from “32 to 96” to “16 to 48.”
transceivers/SMAs in FF665 from 12/48 to 8/32, and the number of clocks/SMAs in
FF665 from 6/12 to 4/8. Section
removed material from introductory paragraph describing the lack of AC coupling.
Table 22, page
2. Modified the power brick connection in
20. Renumbered XGI pins in columns A and B in
23.
“Features,” page
.
Figure
33, corrected ML523 pin for signal XGI_SE_30 from AH32 to AH34.
www.xilinx.com
4. Corrected J113 and J135 column headings in
“18. DDR2 Memory.”
10: Corrected the number of pairs of transceiver SMA
Removed “Power Bus and Switches” diagram from
Corrected ML521 pins in
21. Corrected DDR to DDR2 throughout. Updated ML521
“19. GTP/GTX Transceiver Clock Input SMAs,” page
Table 15
Table
18. Corrected the RS232 and DB9 reference
Figure
Revision
. Corrected CK0N and CK0P pin numbers in
Figure 1, page
R
3. Updated Micron part number in
Corrected numerous pins in
Figure 3
Table
Table
3. Added Platform Cable USB to
Table
11, corrected the number of
for consistency and accuracy.
9. Updated Infineon and
UG225 (v2.1) August 4, 2010
22. Several updates to
Table
19.
Table
Figure
15.
25,
1.