HW-V5-ML525-UNI-G Xilinx Inc, HW-V5-ML525-UNI-G Datasheet - Page 21

• Manufacturer Part Number: HW-V5-ML525-UNI-G
• Description: EVAL PLATFORM ROCKET IO VIRTEX-5
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr
• Type: FPGAr

Specifications of HW-V5-ML525-UNI-G

• Contents: ML52x Platform, Power Supply, Cables and Documentation
• For Use With/related Products: Virtex™-5 LXT
• For Use With: HW-XGI-SCLK-G - MODULE SUPER CLOCKHW-AFX-SMA-SFP - CONVERSION MODULE SMA - SFPHW-AFX-SMA-SATA - CONVERSION MODULE SMA - SATAHW-AFX-SMA-RJ45 - CONVERSION MODULE SMA - RJ45HW-AFX-SMA-NQSL-G - NQSL NELCO QUAD SERIAL LOOPHW-AFX-SMA-HSSDC2 - CONVERSION MODULE SMA - HSSDC2HW-AFX-BERG-SDRAM - EXPANSION MOD SDRAM BERG-SDRAM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ML52x User Guide
UG225 (v2.1) August 4, 2010
18. DDR2 Memory
R
The DDR2 memory interface on the ML52x board consists of four 256-Mbit DDR2 SDRAM
chips (Micron MT47H16M16BG-3:B or Infineon HYB18T256160AF) for a total of 1-Gbit
(128-MB) capacity. The pins conform to the SSTL_1.8V standard and must connect to
SSTL18_II type IOBs on the FPGA. Note that the data strobe pins (DQS*) might need to be
connected to IOBs with digitally-controlled impedance (SSTL18_II_DCI). The designer can
also choose to use differential IOBs (DIFF_SSTL18_II and DIFF_SSTL18_II_DCI) for clock
and data strobe signals.
For more information on the DDR2 memory devices refer to the Micron DDR2 SDRAM
data sheet
Table 15: DDR2 Connections to the DUT
Pin Name
CK0N
CK1N
CAS#
CK0P
CK1P
CKE
BA0
BA1
A10
A11
A12
CS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
[Ref
6].
ML521
Table 15
AC26
AD19
AF18
M24
N21
M21
H24
M26
N26
K26
K25
C18
C14
C13
L24
E25
E26
B19
H22
G22
B20
J24
J26
J25
www.xilinx.com
shows the DDR2 connections to the DUT.
ML523
AE31
AB30
W24
M28
M27
M30
K24
N28
N27
K28
K27
P24
E27
E26
L28
L24
L30
H24
H25
P27
P26
P29
E29
F29
ML525
AH39
AB34
AV40
W33
M39
D37
V36
U36
G37
H36
G36
N39
V34
V35
H39
H38
R34
E38
P35
H35
L39
F36
F37
J36
Detailed Description
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