HIP9011AB Intersil, HIP9011AB Datasheet
HIP9011AB
Specifications of HIP9011AB
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HIP9011AB Summary of contents
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... C) HIP9011AB HIP9011AB -40 to 125 20 Ld SOIC HIP9011ABZ HIP9011ABZ -40 to 125 20 Ld SOIC (See Note) Add “T” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Pinout Pin Descriptions PIN NUMBER DESIGNATION 1 V Five volt power input GND This pin is tied to ground This pin is connected to the internal mid-supply generator and is brought out for bypassing by a ...
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Absolute Maximum Ratings DC Logic Supply -0.5V to 7.0V DD Output Voltage ...
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GND = 0V, Clock Frequency 4MHz ±0.1%, T Electrical Specifications V DD Unless Otherwise Specified (Continued) PARAMETER INPUT AMPLIFIERS CH0 and CH1 High Output Voltage CH0 and CH1 Low Output Voltage Voltage Gain ANTIALIASING FILTER Response 1kHz ...
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Timing Diagrams INT/HOLD CS t CSCH SCK t CSCF SI t SUH SO SYMBOL t Minimum time from CS falling edge to SCK rising edge. CSCH t Minimum time from CS falling edge to SCK falling edge. CSCF t Minimum ...
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V DD VMID 0.022µF GND CH0NI CH1NI CH1IN R in CH1FB R F CH0IN R in CH0FB R F TRANSDUCERS OSCIN 20pF 4MHz OSCOUT 20pF 1MΩ FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9011 IN AN AUTOMOTIVE APPLICATION Description ...
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Circuit Block Description Input Amplifiers Two amplifiers can be selected to interface to the engine sensors. These amplifiers have a typical open loop gain of 100dB, with a typical bandwidth of 2.6MHz. The common mode input voltage range extends to ...
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Integration is enabled by the rising edge of the input control signal INT/HOLD. Within 20µs after the integrate input reaches a logic high level, the output of the integrator will fall to approximately V , 0.125V. The output of the ...
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TABLE 3. FREQUENCY, GAIN, AND INTEGRATOR TIME CONSTANT BIT VALUE PER FREQUENCY FUNCTION (kHz) 0 1.22 1 1.26 2 1.31 3 1.35 4 1.40 5 1.45 6 1.51 7 1.57 8 1.63 9 1.71 10 1.78 11 1.87 12 1.96 ...
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ADDRESS DECODER SI SCK CS FIGURE 5. PROGRAMMABLE REGISTERS AND STATE MACHINE The Digital SPI Block diagram in Figure 5 shows the programming flow of the chip. An eight bit word is received at the SI port. Data is shifted ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...