IDT5T2010 Integrated Device Technology, IDT5T2010 Datasheet

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IDT5T2010

Manufacturer Part Number
IDT5T2010
Description
2.5v Zero Delay Pll Clock Driver Teraclock
Manufacturer
Integrated Device Technology
Datasheet

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FEATURES:
• 2.5 V
• 5 pairs of outputs
• Low skew: 50ps same pair, 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL: up to 250MHz
• HSTL / eHSTL: up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
• Selectable differential or single-ended inputs and ten single-
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
c
of (1-6, 8, 10, 12)
interface
ended outputs
2004
DD
Integrated Device Technology, Inc.
REF
REF
V
REF
V
REF
V
OMODE
RxS
REF2
REF0
REF1
FB/
FB
0
1
0
1
/
/
REF_SEL
0
1
3
DS
/N
1:0
3
2.5V ZERO DELAY PLL
CLOCK DRIVER TERACLOCK™
PD
PE
PLL
FS LOCK
1
DESCRIPTION:
mance computing and data-communications applications. The IDT5T2010
has ten outputs in five banks of two, plus a dedicated differential feedback.
The redundant input capability allows for a smooth change over to a
secondary clock source when the primary clock source is absent.
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
input to ten single-ended outputs. The clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The outputs can be synchronously
enabled/disabled.
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
The IDT5T2010 is a 2.5V PLL clock driver intended for high perfor-
The feedback bank allows divide-by-functionality from 1 to 12 through
The IDT5T2010 features a user-selectable, single-ended or differential
Furthermore, when PE is held high, all the outputs are synchronized with
PLL_EN
0
1
FBF
Divide
Select
Divide
Select
Divide
Select
Divide
Select
Divide
Select
Divide
Select
1F
2F
3F
4F
5F
2:1
2:1
2:1
2:1
2:1
2:1
4sOE
2sOE
3sOE
5sOE
1sOE
INDUSTRIAL TEMPERATURE RANGE
TxS
1
1
2
2
3
3
4
4
5
5
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
FB
FB
0
1
0
1
0
1
0
1
0
1
IDT5T2010
M A Y 2 0 0 3
DSC 5981/24

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IDT5T2010 Summary of contents

Page 1

... ZERO DELAY PLL CLOCK DRIVER TERACLOCK™ DESCRIPTION: The IDT5T2010 is a 2.5V PLL clock driver intended for high perfor- mance computing and data-communications applications. The IDT5T2010 has ten outputs in five banks of two, plus a dedicated differential feedback. The redundant input capability allows for a smooth change over to a secondary clock source when the primary clock source is absent ...

Page 2

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK PIN CONFIGURATION 1sOE OMODE REF_ D GND V DD SEL REF 1 E REF REF1 REF 0 F REF REF0 REF2 PLL_ ...

Page 3

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK PIN CONFIGURATION 1 REF_SEL REF 3 1 REF / REF1 REF 5 0 REF / REF0 7 FB FB/V 8 REF2 PLL_EN RxS 14 TxS 15 LOCK INDUSTRIAL TEMPERATURE RANGE GND VFQFPN TOP VIEW ...

Page 4

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK ABSOLUTE MAXIMUM RATINGS Symbol Description ( Power Supply Voltage DDQ DD V Input Voltage I V Output Voltage O (3) V Reference Voltage REF T Junction Temperature J T Storage Temperature STG NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 5

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK PIN DESCRIPTION, CONTINUED Symbol I/O Type Description (1) REF_SEL I LVTTL Reference clock select. When LOW, selects REF nsOE Synchronous output enable. When nsOE is HIGH, nQ (1) I LVTTL LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the is stopped in a HIGH/LOW state ...

Page 6

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK EXTERNAL DIFFERENTIAL FEEDBACK By providing a dedicated external differential feedback, the IDT5T2010 gives users flexibility with regard to divide selection. The FB and FB/ V signals are compared with the input REF REF2 signals at the phase detector in order to drive the VCO. Phase differ- ences cause the VCO of the PLL to adjust upwards or downwards accordingly ...

Page 7

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK INPUT/OUTPUT SELECTION Input 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2 ...

Page 8

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage IN (2, Differential Voltage DIF V DC Common Mode Input Voltage ...

Page 9

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL Symbol Parameter V Input Signal Swing (1) DIF V Differential Input Signal Crossing Point X V Input Timing Measurement Reference Level THI ( Input Signal Edge Rate R F NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the V specification under actual use conditions ...

Page 10

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS Symbol Parameter I Quiescent V Power Supply Current DDQ DD I Quiescent V Power Supply Current DDQQ DDQ I Power Down Current DDPD I Dynamic V Power Supply DDD DD Current per Output I Dynamic V Power Supply ...

Page 11

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR (1) LVEPECL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage Common Mode Input Voltage CM V Single-Ended Reference Voltage ...

Page 12

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V (1) LVTTL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage IN (2) Single-Ended Inputs V DC Input HIGH Input LOW ...

Page 13

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS Symbol Parameter I Quiescent V Power Supply Current DDQ DD I Quiescent V Power Supply Current DDQQ DDQ I Power Down Current DDPD I Dynamic V Power Supply DDD DD Current per Output I Dynamic V Power Supply ...

Page 14

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V (1) LVTTL Symbol Parameter Input Characteristics I Input HIGH Current IH I Input LOW Current IL V Clamp Diode Voltage Input Voltage IN Single-Ended Inputs ( Input HIGH Input LOW IL Differential Inputs ...

Page 15

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS Symbol Parameter I Quiescent V Power Supply Current DDQ DD I Quiescent V Power Supply Current DDQQ DDQ I Power Down Current DDPD I Dynamic V Power Supply DDD DD Current per Output I Dynamic V Power Supply ...

Page 16

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Symbol Parameter F VCO Frequency Range NOM t Reference Clock Pulse Width HIGH or LOW RPW t Feedback Input Pulse Width HIGH or LOW FPW Output Matched Pair Skew Output Skew (Rise-Rise, Fall-Fall, Nominal) ...

Page 17

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK AC DIFFERENTIAL INPUT SPECIFICATIONS Symbol Parameter t Reference/Feedback Input Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs) W Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs) HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL V AC Differential Voltage (3) DIF V AC Input HIGH (4,5) IH (4,6) ...

Page 18

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK (1) AC TIMING DIAGRAM REF REF OTHER Q INVERTED Q Q DIVIDED DIVIDED BY 4 NOTE: 1. The AC TIMING DIAGRAM applies edge of REF , and the positive edges of the divide-by-2 and divide-by-4 signals align. [1:0] t RPWL t RPWH ...

Page 19

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK JITTER AND OFFSET TIMING WAVEFORMS [1:0] FB REF [1:0] REF [1: NOTE: 1. Diagram for and TxS/RxS = [1: cycle n cycle jit(cc) cycle n cycle n+1 Cycle-to-Cycle jitter t (Ø) (Ø)n (Ø ...

Page 20

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK [1: [1:0] FB NOTE: 1. 1/fo = average period NOTE: 1. 1/fo = average period. t cycle jit(per) = cycle n Period jitter t t half period n+1 half period jit(hper) = half period n ...

Page 21

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK TEST CIRCUITS AND CONDITIONS Pulse Generator DIFFERENTIAL INPUT TEST CONDITIONS Symbol NOTE: 1. This input configuration is used for all input interfaces. For single-ended testing, the REF mode, the V 3 inch, ~50 Transmission Line 3 inch, ~50 ...

Page 22

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK V V DDQ DD REF [1:0] nQ [1:0] D.U.T. FB QFB QFB FB SW1 Test Circuit for Outputs OUTPUT TEST CONDITIONS Symbol V = 2.5V ± 0. Interface Specified DDQ 100 R2 100 THO DDQ SW1 TxS = MID or HIGH TxS = LOW V DDQ ...

Page 23

... IDT5T2010 2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK ORDERING INFORMATION IDT XXXXX XX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 X Package I -40°C to +85°C (Industrial) Plastic Ball Grid Array BB Thermally Enhanced Plastic Very Fine NL Pitch Quad Flat No Lead Package 5T2010 2 ...

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