AT90PWM3B-16SU Atmel, AT90PWM3B-16SU Datasheet
AT90PWM3B-16SU
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AT90PWM3B-16SU Summary of contents
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... Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B 4317H–AVR–12/06 ...
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... History Product AT90PWM2 AT90PWM3 AT90PWM2B AT90PWM3B This datasheet deals with product characteristics of AT90PW2 and AT90WM3. It will be updated as soon as characterization will be done. 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max val- ues will be available after the device is characterized ...
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Pin Configurations Figure 3-1. (TXD/DALI/OC0A/SS/MOSI_A) PD3 (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 Figure 3-2. (ADC1/RXD/DALI/ICP1A/SCK_A) PD4 4317H–AVR–12/06 SOIC 24-pin Package (PSCOUT00/XCK/SS_A) PD0 (RESET/OCD) PE0 (PSCIN0/CLKO) PD1 (PSCIN2/OC1A/MISO_A) PD2 VCC GND (MISO/PSCOUT20) PB0 (MOSI/PSCOUT21) PB1 (OC0B/XTAL1) PE1 (ADC0/XTAL2) PE2 SOIC 32-pin Package (PSCOUT00/XCK/SS_A) PD0 ...
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Figure 3-3. (PSCIN2/OC1A/MISO_A) PD2 (TXD/DALI/OC0A/SS/MOSI_A) PD3 AT90PWM2/2B/3/3B 4 QFN32 (7*7 mm) Package. AT90PWM3/3B QFN (PSCIN1/OC1B) PC1 3 VCC 4 GND 5 (T0/PSCOUT22) PC2 6 (T1/PSCOUT23) PC3 7 (MISO/PSCOUT20) PB0 8 24 PB4 (AMP0+) 23 PB3 (AMP0-) 22 ...
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Pin Descriptions : Table 3-1. Pin out description S024 Pin SO32 Pin QFN32 Pin Number Number Number ...
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Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number ...
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Table 3-1. Pin out description (Continued) S024 Pin SO32 Pin QFN32 Pin Number Number Number Overview The AT90PWM2/2B/3/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in ...
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Block Diagram Figure 4-1. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in ...
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... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90PWM2 powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90PWM2/3 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits ...
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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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AVR CPU Core 5.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...
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Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 5.5 General Purpose Register File The Register File is optimized for the ...
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Figure 5-3. X-register Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack Pointer The Stack is mainly used for storing ...
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Figure 5-4 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ...
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BOOTRST Fuse, see gramming” on page 5.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 5.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is ...
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Memories This section describes the different memories in the AT90PWM2/2B/3/3B. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM2/2B/3/3B features an EEPROM Memory for data storage. All three ...
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SRAM Data Memory Figure 2 The AT90PWM2/2B/3/ complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from ...
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Figure 3. On-chip Data SRAM Access Cycles 6.3 EEPROM Data Memory The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has ...
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The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address ...
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EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 1. EEPROM Mode Bits EEPM1 • Bit 3 – EERIE: ...
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When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData 4317H–AVR–12/06 ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...
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I/O Memory The I/O space definition of the AT90PWM2/2B/3/3B is shown in 333. All AT90PWM2/2B/3/3B I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between ...
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General Purpose I/O Register 3– GPIOR3 Bit Read/Write Initial Value AT90PWM2/2B/3/ GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 R/W R/W R/W R GPIOR3 R/W R/W ...
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System Clock 7.1 Clock Systems and their Distribution Figure 7-1 need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described ...
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Figure 7-2. 7.1.1 CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the ...
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ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 7.2 ...
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Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. The Watchdog Oscillator is used for timing this ...
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The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Crystal Oscillator Operating Modes CKSEL3..1 100 101 110 111 Notes: The ...
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Register and thereby automatically calibrates the RC Oscillator and 25°C, this calibration gives a frequency of 8 MHz ± 1%. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1% accuracy, ...
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The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6.. ...
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Figure 7-4. Figure 7-5. XTAL1 XTAL2 7.6.2 PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero. ...
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If PLLF is clear, the PLL output is 32Mhz. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. ...
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Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to 38 for details. 7.9 Clock Output Buffer When the CKOUT Fuse is programmed, the system ...
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Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Timer/Counters, Watchdog, and the interrupt system to continue operating. This ...
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Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Sleep Mode Idle ADC Noise Reduction Power- ...
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Writing a logic one to this bit reduces the consumption of the PSC1 by stopping the clock to this module. When waking up the PSC1 again, the PSC1 should be re initialized to ensure proper operation. • Bit 5 - ...
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Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always ...
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System Control and Reset 9.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
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Figure 9-1. Table 9-1. Symbol V POT V RST t RST Notes: 9.0.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger ...
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Figure 9-2. Figure 9-3. 9.0.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Shorter pulses are not guaranteed to generate a reset. When the ...
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Brown-out Detection AT90PWM2/2B/3/3B has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The ...
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Figure 9-5. 9.0.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 51 ...
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This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a ...
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Watchdog Timer AT90PWM2/2B/3/3B has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example WDT_Prescaler_Change: C Code Example void WDT_Prescaler_Change(void Note: Note: The Watchdog Timer should be reset before ...
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Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog ...
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Table 9-6. WDP3 4317H–AVR–12/06 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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Interrupts ...
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Table 16. Reset and Interrupt Vectors Vector No Notes: Table 17 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit ...
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When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most ...
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Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled ...
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I/O-Ports 11.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General Digital I/O Note: 11.2.1 Configuring the Pin Each port pin consists ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock ...
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Assembly Code Example C Code Example unsigned char i; Note: 11.2.5 ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified alternate functions. The overriding signals may not be present in all port pins, ...
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Table 19. Generic Description of Overriding Signals for Alternate Functions Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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ADC6/INT2 – Bit 5 ADC6, Analog to Digital Converter, input channel 6 INT2, External Interrupt source 2. This pin can serve as an External Interrupt source to the MCU. • APM0+ – Bit 4 AMP0+, Analog Differential Amplifier 0 ...
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Table 21 Figure 11-5 on page Table 21. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 22. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PUOE PUOV ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 23. Port C Pins Alternate Functions The alternate pin configuration is as follows: • D2A – Bit 7 D2A, Digital to Analog output ...
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PCSIN1, PSC 1 Digital Input. OC1B, Output Compare Match B output: This pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDC1 set “one”) to serve this ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 26. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: ...
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ACMP2, Analog Comparator 1 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Ana- log Comparator. • ADC1/RXD/ICP1/SCK_A – Bit 4 ADC1, ...
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XCK, USART External clock. The Data Direction Register (DDD0) controls whether the clock is output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when the USART oper- ates in Synchronous mode. SS_A: Slave Port Select input. ...
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Table 28. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 11.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 29. Port ...
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XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin. OC0B, Output Compare Match B output: This ...
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Initial Value 11.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value 11.4.4 Port C Data Register – PORTC Bit Read/Write Initial Value 11.4.5 Port C Data Direction Register – DDRC Bit Read/Write Initial Value 11.4.6 Port C ...
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Port E Data Direction Register – DDRE Bit Read/Write Initial Value 11.4.12 Port E Input Pins Address – PINE Bit Read/Write Initial Value 4317H–AVR–12/ – – – – ...
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External Interrupts The External Interrupts are triggered by the INT3:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT3:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. ...
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Note: 12.0.2 External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bits 3..0 – INT3 – INT0: External Interrupt Request Enable When an INT3 – INT0 bit is written to one and the I-bit in ...
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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.0.1 Internal Clock Source The Timer/Counter can be clocked directly ...
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Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f sampling, the maximum ...
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Timer 1 capture function has two possible inputs ICP1A (PD4) and ICP1B (PB6). The selection is made thanks to ICPSEL1 bit as described in Table 32. ICPSEL1 ICPSEL1 0 1 • Bit 0 – PSRSYNC: Prescaler Reset When this bit ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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The definitions in Table 33. Definitions BOTTOM MAX TOP 14.1.2 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt ...
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Tn top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 ...
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Figure 14-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com- pare (FOC0x) strobe bits in ...
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PWM refer to A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced ...
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Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
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PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. Figure 14-6. Fast PWM Mode, Timing Diagram TCNTn OCn OCn Period The Timer/Counter Overflow Flag (TOV0) is set each time the ...
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Phase Correct PWM Mode The phase correct PWM mode (WGM02 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly ...
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OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). ...
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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 14-10 mode and PWM mode, where OCR0A is TOP. Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ...
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Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O ...
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These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data ...
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Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form generation to be used, see unit are: Normal ...
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Therefore it is the value present in the COM0B1:0 bits that determines the effect of the forced compare. A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. ...
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Output Compare Register B – OCR0B Bit Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, ...
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The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor- responding interrupt handling vector. Alternatively, OCF0A is cleared by ...
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Timer/Counter1 with PWM The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.1.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in ...
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The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: ; Save global interrupt ...
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The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
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Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk T n TOP BOTTOM The 16-bit counter ...
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Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ...
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For more information on how to access the 16-bit registers refer to on page 15.5.1 Input Capture Trigger Source The trigger sources for the Input Capture unit arethe Input Capture pin (ICP1A & ICP1B). Be aware that changing trigger source ...
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I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP ...
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Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare Register in the same ...
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Figure 15-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx clk The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction ...
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PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page For detailed ...
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TOP value. How- ever, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be ...
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Figure 15-7. Fast PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn Flag is set at the same timer clock cycle as ...
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The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM ...
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Figure 15-8. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ...
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The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx ...
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Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). ...
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The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal ...
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Figure 15-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) and ICFn Figure 15-13 Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 15.10 16-bit Timer/Counter Register Description 15.10.1 Timer/Counter1 Control Register A – ...
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I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond- ing to the OCnA or OCnB pin must be set in order to enable the output driver. When the OCnA or OCnB is connected ...
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Note: • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- ...
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This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit ...
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FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear ...
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Input Capture Register 1 – ICR1H and ICR1L Bit Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 Bit Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input ...
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Power Stage Controller – (PSC0, PSC1 & PSC2) The Power Stage Controller is a high performance waveform controller. 16.1 Features • PWM waveform generation function (2 complementary programmable outputs) • Dead time control • Standard mode ...
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PSC Description Figure 16-1. Power Stage Controller Block Diagram Note: The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to count up and count down from ...
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PSC2 Distinctive Feature Figure 16-2. PSC2 versus PSC1&PSC0 Block Diagram Note: PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23 can duplicate PSCOUT20 ...
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Output Polarity The polarity “active high” or “active low” of the PSC outputs is programmable. All the timing dia- grams in the following examples are given in the “active high” polarity. 16.4 Signal Description Figure 16-3. PSC External Block ...
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Input Description Table 47. Internal Inputs Name OCRnRB[1 1:0] OCRnSB[1 1:0] OCRnRA[1 1:0] OCRnSA[1 1:0] OCRnRB[1 5:12] CLK I/O CLK PLL SYnIn StopIn Note: Table 48. Block Inputs Name PSCINn from A C 16.4.2 Output Description Table 49. Block ...
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Table 50. Internal Outputs Name SYnOut PICRn [11:0] IRQPSCn PSCnASY StopOut Note: 16.5 Functional Description 16.5.1 Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output ...
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Figure 16-5. Cycle Presentation in Centered Mode Centered Mode Ramps illustrate the output of the PSC counter included in the waveform generators. Centered Mode is like a one ramp mode which count down up and down. Notice that the update ...
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PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = OCRnRAH/L * 1/Fclkpsc On-Time 1 = OCRnRBH/L * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time ...
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Figure 16-8. PSCn0 & PSCn1 Basic Waveforms in One Ramp mode PSC Counter PSCOUTn0 PSCOUTn1 On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time ...
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Figure 16-9. PSCn0 & PSCn1 Basic Waveforms in Center Aligned Mode On-Time OCRnSAH/L * 1/Fclkpsc On-Time (OCRnRBH/L - OCRnSBH 1/Fclkpsc Dead-Time = (OCRnSBH/L - OCRnSAH/L) * 1/Fclkpsc PSC Cycle ...
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Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L ...
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The resulting output frequency is the average of the frequencies in the frame. The fractional divider (d) is given by OCRnRB[15:12]. The PSC output period is directly equal to the PSCOUTn0 On Time + Dead Time (OT0+DT0) ...
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Frequency distribution The frequency modulation is done by switching two frequencies consecutive cycle frame. These two frequencies are f frequency and f in the frame is (d-16) and the number of f uted in the frame ...
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Modes of Operation 16.7.2.1 Normal Mode The simplest mode of operation is the normal mode. See The active time of PSCOUTn0 is given by the OT0 value. The active time of PSCOUTn1 is given by the OT1 value. Both ...
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PSC Inputs Each part PSC has its own system to take into account one PSC input. According to PSC n Input A/B Control Register (see description has a Retrigger or Fault input. This system A ...
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Figure 16-15. PSCOUTn0 retriggered by PSCn Input A (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Note: Figure 16-16. PSCOUTn0 retriggered by PSCn Input A (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input A (high level) ...
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Figure 16-17. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Note: Figure 16-18. PSCOUTn1 retriggered by PSCn Input B (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input B (high level) ...
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Figure 16-19. Burst Generation PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 16.8.4 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. 16.8.4.1 Filter Enable If the “Filter Enable” bit ...
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If PELEVnx bit set, the significant edge of PSCn Input rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - 4-ramp mode, PSCn Input A is ...
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PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 16-20. PSCn behaviour versus PSCn Input A in Fault Mode 1 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is ...
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PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait Figure 16-22. PSCn behaviour versus PSCn Input A in Fault Mode 2 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is take ...
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PSC Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 16-24. PSCn behaviour versus PSCn Input A in Mode 3 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is taken ...
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Figure 16-26. PSC behaviour versus PSCn Input A or Input B in Mode 4 DT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 16-27. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4 DT0 ...
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PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 16-29. PSC behaviour versus PSCn Input A in Fault Mode 6 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Used in Fault mode ...
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PSC Input Mode 8: Edge Retrigger PSC Figure 16-31. PSC behaviour versus PSCn Input A in Mode 8 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurence of significative edge of retriggering input. ...
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PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurence of significative edge ...
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PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output Figure 16-35. PSC behaviour versus PSCn Input A in Mode 14 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the ...
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Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes.. Table 53. Available Input Modes according to ...
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PSC2 Outputs 16.19.1 Output Matrix PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and PSCOUT21 binary value for each ramp. Table 54. Output Matrix versus ramp number PSCOUT20 PSCOUT21 PSCOUT2m ...
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Analog Synchronization PSC generates a signal to synchronize the sample and hold; synchronisation is mandatory for measurements. This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs. In center aligned mode, OCRnRAH/L is ...
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If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1. PRUNn and PARUNn bits are located in PCTLn register. on page 164. See “PSC 1 Control Register – PCTL1” on page 166. ...
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Table 55. Output Clock versus Selection and Prescaler PCLKSELn 16.24 Interrupts ...
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PSC Register Definition Registers are explained for PSC0. They are identical for PSC1. For PSC2 only different registers are described. 16.25.1 PSC 0 Synchro and Output Configuration – PSOC0 Bit Read/Write Initial Value 16.25.2 PSC 1 Synchro and Output ...
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Table 58. Synchronization Source Description in Centered Mode PSYNCn1 • Bit 3 – POEN2D : PSCOUT23 Output Enable (PSC2 only) When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port. ...
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Output Compare SB Register – OCRnSBH and OCRnSBL Bit Read/Write Initial Value 16.25.7 Output Compare RB Register – OCRnRBH and OCRnRBL Bit Read/Write Initial Value Note : according to PSC number. The Output Compare ...
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Bit 6 - PALOCKn: PSC n Autolock When this bit is set, the Output Compare Registers RA, SA, SB, the Output Matrix POM2 and the PSC Output Configuration PSOCn can be written without disturbing the PSC cycles. The update ...
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Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select This two bits select the PSC input clock division factor. All generated waveform will be modified by this factor. Table 60. PSC 0 Prescaler Selection PPRE01 ...
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PSC 1 Control Register – PCTL1 Bit Read/Write Initial Value • Bit 7:6 – PPRE11:0 : PSC 1 Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table ...
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PSC 2 Control Register – PCTL2 Bit Read/Write Initial Value • Bit 7:6 – PPRE21:0 : PSC 2 Prescaler Select This two bits select the PSC input clock division factor.All generated waveform will be modified by this factor. Table ...
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PSC n Input A Control Register – PFRCnA Bit Read/Write Initial Value 16.25.15 PSC n Input B Control Register – PFRCnB Bit Read/Write Initial Value The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A ...
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PRFMnx3:0 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 16.25.16 PSC 0 Input Capture Register – PICR0H and PICR0L Bit Read/Write Initial Value 16.25.17 PSC 1 Input Capture Register – PICR1H and PICR1L Bit Read/Write Initial Value ...
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This temporary register is shared by all the other 16-bit or 12-bit registers. Note for AT90PWM2/3 : This register is read only and a write to this register is not allowed. 16.26 PSC2 Specific Register ...
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Read/Write Initial Value 16.26.4 PSC2 Interrupt Mask Register – PIM2 Bit Read/Write Initial Value • Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable When this bit is set, the PSEIn bit (if set) generate an interrupt. • ...
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Bit 6 – POACnA : PSC n Output A Activity (not implemented on AT90PWM2/3) This bit is set by hardware each time the output PSCOUTn0 changes from from Must be cleared by ...
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Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90PWM2/2B/3/3B and peripheral devices or between several AVR devices. The AT90PWM2/2B/3/3B SPI includes the following features: 17.1 Features • Full-duplex, Three-wire Synchronous ...
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SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave ...
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Table 65. SPI Pin Overrides Pin MISO SCK SS Note: The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual ...
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Assembly Code Example SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi out ; Enable SPI, Master, set clock rate fck/16 ldi out ret SPI_MasterTransmit: ; Start transmission of data (r16) out Wait_Transmit: ; Wait for transmission complete ...
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Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 4317H–AVR–12/06 (1) ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret ; Wait ...
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SS Pin Functionality 17.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
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Note that programming port are always located on alternate SPI port. 17.2.4 SPI Control Register – SPCR Bit Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if ...
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These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk the following table: Table 68. Relationship Between SCK and the ...
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SPI Data Register – SPDR Bit Read/Write Initial Value • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to ...
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Figure 17-4. SPI Transfer Format with CPHA = 1 AT90PWM2/2B/3/3B 182 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) ...
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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: 18.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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Overview A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. Figure 18-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts ...
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Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSEL bit in ...
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Table 70 the UBRR value for each mode of operation using an internally generated clock source. Table 70. Equations for Calculating Baud Rate Register Setting Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) ...
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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...
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Figure 18-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing ...
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Note that the TXC flag must be cleared before each transmission (before UDR is written used for this purpose. The following simple USART initialization code examples show ...
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XCK pin will be overridden and used as transmission clock. 18.6.1 Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data ...
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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following ...
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Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether ...
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Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDR I/O location. The following code example shows a simple USART receive function based on polling of ...
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Assembly Code Example USART_Receive: ; Wait for data to be received sbis UCSRA, RXC0 rjmp USART_Receive ; Get status and 9th bit, then data from buffer lds lds r17, UCSRB lds r16, UDR ; If error, return -1 andi r18,(1<<FE0)|(1<<DOR0)|(1<<UPE0) ...
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Receive Complete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data ...
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Figure 18-5. Data OverRun example RxD DOR RxC Software Access to Receive buffer The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the ...
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Assembly Code Example USART_Flush: C Code Example void USART_Flush( void ) { } Note: 18.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used ...
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Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov- ery logic is synchronized ...
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Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, ...
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Table 3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides ...