AT90PWM3B-16SU Atmel, AT90PWM3B-16SU Datasheet - Page 276

• Manufacturer Part Number: AT90PWM3B-16SU
• Description: IC MCU AVR RISC 8K FLASH 32-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• On-chip Dac: 1-chx10-bit
• Controller Family/series: AVR PWM
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25. Memory Programming
25.1
276
Program And Data Memory Lock Bits
AT90PWM2/2B/3/3B
For details about these two section, see
and
Table 42. Explanation of Different Variables used in
pointer
Note:
The AT90PWM2/2B/3/3B provides six Lock bits which can be left unprogrammed (“1”) or can be
programmed (“0”) to obtain the additional features listed in
erased to “1” with the Chip Erase command.
Table 43. Lock Bit Byte
Variable
PCMSB
PAGEMSB
ZPCMSB
ZPAGEMSB
PCPAGE
PCWORD
BLB12
BLB11
BLB02
BLB01
LB2
LB1
“RWW – Read-While-Write Section” on page 264
Lock Bit Byte
1. Z15:Z13: always ignored
Z0: should be zero for all SPM commands, byte select for the LPM instruction.
See
Z-pointer during Self-Programming.
“Addressing the Flash During Self-Programming” on page 269
PC[11:5]
PC[4:0]
11
4
(1)
Corresponding
Bit No
Z-value
7
6
5
4
3
2
1
0
Z12:Z6
Z5:Z1
Z12
Z5
(1)
“NRWW – No Read-While-Write Section” on page 264
Description
–
–
Boot Lock bit
Boot Lock bit
Boot Lock bit
Boot Lock bit
Lock bit
Lock bit
Description
Most significant bit in the Program Counter. (The
Program Counter is 12 bits PC[11:0])
Most significant bit which is used to address the
words within one page (32 words in a page requires
5 bits PC [4:0]).
Bit in Z-register that is mapped to PCMSB. Because
Z0 is not used, the ZPCMSB equals PCMSB + 1.
Bit in Z-register that is mapped to PAGEMSB.
Because Z0 is not used, the ZPAGEMSB equals
PAGEMSB + 1.
Program counter page address: Page select, for
page erase and page write
Program counter word address: Word select, for
filling temporary buffer (must be zero during page
write operation)
Figure 24-3
Table
Default Value
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
44. The Lock bits can only be
and the Mapping to the Z-
for details about the use of
4317H–AVR–12/06