PIC18F2410-I/ML Microchip Technology, PIC18F2410-I/ML Datasheet - Page 219

• Manufacturer Part Number: PIC18F2410-I/ML
• Description: IC PIC MCU FLASH 8KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2410-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• For Use With: XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.6
Figure 18-4 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
Figure 18-5 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are set to ‘010’ and selecting a 4 T
time before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 18-4:
FIGURE 18-5:
© 2009 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO bit
1
conversion
T
Set GO bit
CY
A/D Conversions
T
Holding capacitor is disconnected from analog input (typically 100 ns)
ACQT
Acquisition
Automatic
- T
2
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
sample.
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
(Holding capacitor is disconnected)
Conversion starts
AD
b8
1
This
3 T
b9
AD
2
b7
AD
means
4 T
acquisition
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
AD
b8
3
AD
AD
b6
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
the
AD
b7
b5
4
6 T
T
AD
b4
5
b6
AD
7 T
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
18.7
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier, as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measure values.
Cycles
Note:
AD
b5
b3
AD
6
8
wait is required before the next acquisition can be
PIC18F2X1X/4X1X
T
Discharge
b4
AD
b2
7
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
9 T
AD
b3
8
b1
10
T
AD
ACQ
b0
b2
9
ACQ
11
= 0)
T
= 4 T
AD
10
Discharge
b1
1
AD
DS39636D-page 221
b0
11
)
T
Discharge
AD
1