PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 105
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PIC18C801-I/PT
Manufacturer Part Number
PIC18C801-I/PT
Description
IC PIC MCU ROMLESS 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C801-I/PT
Core Size
8-Bit
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Number Of I /o
37
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
67
Ram Memory Size
1.5KB
Cpu Speed
6.25MIPS
No. Of Timers
4
Program Memory Size
EXT
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
47
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C801I/PT
Available stocks
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Quantity
Price
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Manufacturer:
Microchip Technology
Quantity:
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Manufacturer:
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- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 105 of 320
- Download datasheet (6Mb)
9.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output ( i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATB register
read and write the latched output value for PORTB.
EXAMPLE 9-2:
FIGURE 9-3:
CLRF
CLRF
MOVLW
MOVWF
Data Bus
WR LATB
or
WR PORTB
WR TRISB
RBPU
RBx/INTx
Set RBIF
2001 Microchip Technology Inc.
From other
RB7:RB4 pins
Note 1: I/O pins have diode protection to V
(2)
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
PORTB, TRISB and LATB
Registers
and clear the RBPU bit (INTCON2 register).
PORTB
LATB
0CFh
TRISB
RD TRISB
RD LATB
RD PORTB
Data Latch
TRIS Latch
D
D
CK
CK
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB3:RB0 as inputs
; RB5:RB4 as outputs
; RB7:RB6 as inputs
RB7:RB4 PINS BLOCK
DIAGRAM
Q
Q
Q
Q
Latch
EN
EN
D
DD
D
TTL
Input
Buffer
and V
RD PORTB
V
P
DD
SS
Advance Information
Weak
Pull-up
I/O pin
.
Buffer
Q1
Q3
ST
(1)
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2 register). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Pin RB3 is multiplexed with the CCP input/output. The
weak pull-up for RB3 is disabled when the RB3 pin is
configured as CCP pin. By disabling the weak pull-up
when pin is configured as CCP, allows the remaining
weak pull-up devices of PORTB to be used while the
CCP is being used.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON register).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
Clear flag bit RBIF.
PIC18C601/801
DS39541A-page 105
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