PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 70

• Manufacturer Part Number: PIC18C801-I/PT
• Description: IC PIC MCU ROMLESS 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/PT

• Core Size: 8-Bit
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 67
• Ram Memory Size: 1.5KB
• Cpu Speed: 6.25MIPS
• No. Of Timers: 4
• Program Memory Size: EXT
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801I/PT

PIC18C601/801
5.4
Chip select signals are used to select regions of exter-
nal memory and I/O devices for access. The
PIC18C801 has three chip selects and all are program-
mable. The chip select signals are CS1, CS2 and
CSIO. CS1 and CS2 are general purpose chip selects
that are used to enable large portions of program mem-
ory. CSIO is used to enable external I/O expansion.
The PIC18C601uses two of these programmable chip
selects: CS1 and CSIO.
REGISTER 5-2:
REGISTER 5-3:
DS39541A-page 70
Chip Selects
bit 7-0
bit 7-0
CSEL2 REGISTER
CSELIO REGISTER
bit 7
CSL<7:0>: Chip Select 2 Address Decode bits
XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program
00h = CS2 is inactive
Legend:
R = Readable bit
- n = Value at POR
bit7
CSIO<7:0>: Chip Select IO Address Decode bits
XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program
00h = CSIO is inactive
Legend:
R = Readable bit
- n = Value at POR
CSIO7
R/W-1
R/W-1
CSL7
counter. If PC<20:13>
counter. If PC<20:13>
If PC<20:13> < CSL<7:0>, CS2 is high.
CSIO6
R/W-1
R/W-1
CSL6
Advance Information
CSIO5
R/W-1
R/W-1
CSL5
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
CSL<7:0> register, then the CS2 signal is low.
CSIO<7:0>, then the CSIO signal is low. If not, CSIO is high.
CSIO4
R/W-1
R/W-1
CSL4
Two SFRs are used to control the chip select signals.
These are CSEL2 and CSELIO (see Register 5-2 and
Register 5-3). A chip select signal is asserted low when
the CPU makes an access to a dedicated range of
addresses specified in the chip select registers, CSEL2
and CSELIO. The 8-bit value found in either of these
registers is decoded as one of 256, 8K banks of pro-
gram memory. If both chip select registers are 00h, all
of the chip select signals are disabled and their corre-
sponding pins are configured as I/O. Since the last 512
bytes of program memory are dedicated to internal pro-
gram RAM, the chip select signals will not activate if the
program memory address falls in this range.
CSIO3
R/W-1
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-1
CSL3
CSIO2
R/W-1
R/W-1
CSL2
2001 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
CSIO1
R/W-1
R/W-1
CSL1
CSIO0
R/W-1
R/W-1
CSL0
bit 0
bit0