PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 28

• Manufacturer Part Number: PIC18C801-I/PT
• Description: IC PIC MCU ROMLESS 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/PT

• Core Size: 8-Bit
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 67
• Ram Memory Size: 1.5KB
• Cpu Speed: 6.25MIPS
• No. Of Timers: 4
• Program Memory Size: EXT
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801I/PT

PIC18C601/801
FIGURE 2-10:
2.6.3
If both SCS0 and SCS1 are set to ‘1’ simultaneously,
the SCS0 bit has priority over the SCS1 bit. This means
that the low power option will take precedence over the
PLL option. If both bits are cleared simultaneously, the
system clock will come from OSC1, after a T
out. If only the SCS0 bit is cleared, the system clock will
come from the PLL output, following T
time.
TABLE 2-3:
2.7
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP, will increase the cur-
TABLE 2-4:
DS39541A-page 28
OSC Mode
RC
EC
LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level
SCS1
Note:
Note: RC oscillator mode assumed.
Program Counter
0
0
1
1
(OSCCON<0>)
Internal System
Effects of SLEEP Mode on the
On-Chip Oscillator
T1OSI
OSC1
OSC2
SCS0
Clock
SCS0
See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
SCS0, SCS1 PRIORITY
Floating, external resistor should pull high
Floating
0
1
0
1
SCS0, SCS1 PRIORITY
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Ext Oscillator OSC1
Timer1 Oscillator
HS + PLL
Timer1 Oscillator
Q3
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Clock Source
PC
OSC1 Pin
Q4
OST
Advance Information
OST
and T
Q1
time-
PLL
T
1
OSC
T
rent consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.8
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see Section 3.0 RESET.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of T
#33) on power-up only. The second timer is the Oscil-
lator Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable.
PIC18C601/801 devices provide a configuration bit,
PWRTEN in CONFIG2L register, to enable or disable
the Power-up Timer. By default, the Power-up Timer is
enabled.
With the PLL enabled (HS4 oscillator mode), the time-out
sequence following a Power-on Reset is different from
other oscillator modes. The time-out sequence is as fol-
lows: the PWRT time-out is invoked after a POR time
delay has expired, then, the Oscillator Start-up Timer
(OST) is invoked. However, this is still not a sufficient
amount of time to allow the PLL to lock at high frequen-
cies. The PWRT timer is used to provide an additional
time-out, called T
ample time to lock to the incoming clock frequency.
T
1
2
P
At logic low
At logic low
3
PC + 2
4
Power-up Delays
T
SCS
5
6
PLL
7
(parameter #7), to allow the PLL
8
OSC2 Pin
Q1 Q2
2001 Microchip Technology Inc.
Q3 Q4 Q1 Q2 Q3
PWRT
PC + 4
(parameter
Q4