PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 183
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PIC18C801-I/PT
Manufacturer Part Number
PIC18C801-I/PT
Description
IC PIC MCU ROMLESS 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C801-I/PT
Core Size
8-Bit
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Core Processor
PIC
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Number Of I /o
37
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
67
Ram Memory Size
1.5KB
Cpu Speed
6.25MIPS
No. Of Timers
4
Program Memory Size
EXT
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
47
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C801I/PT
Available stocks
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Quantity
Price
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Manufacturer:
Microchip Technology
Quantity:
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- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 183 of 320
- Download datasheet (6Mb)
16.2
In this mode, data is transmitted in non-return-to-zero
(NRZ) format. Data consists of one START bit, eight or
nine data bits and one STOP bit. Data is transmitted in
serial fashion with LSb first. An on-chip 8-bit baud rate
generator can be programmed to generate the desired
baud rate. The baud rate generator produces a clock,
either x16 or x64 of the bit shift rate, depending on the
BRGH bit (TXSTA register). USART does not automat-
ically calculate the parity bit for the given data byte. If
parity is to be transmitted, USART must be pro-
grammed to transmit nine bits and software must set/
clear ninth data bit as parity bit. Asynchronous mode is
stopped during SLEEP.
Asynchronous mode is selected by clearing the SYNC
bit (TXSTA register).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
16.2.1
The USART transmitter block diagram is shown in
Figure 16-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The TSR register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the STOP
bit has been transmitted from the previous load. As
soon as the STOP bit is transmitted, the TSR is loaded
with new data from the TXREG register (if available).
FIGURE 16-1:
2001 Microchip Technology Inc.
Note:
I/O pins have diode protection to V
USART Asynchronous Mode
USART ASYNCHRONOUS
TRANSMITTER
TXIE
Interrupt
USART TRANSMIT BLOCK DIAGRAM
TXEN
TXIF
Baud Rate Generator
SPBRG
Baud Rate CLK
DD
and V
MSb
(8)
SS
Advance Information
.
TX9D
TXREG Register
TSR Register
TX9
8
Data Bus
Once the TXREG register transfers the data to the TSR
register (occurs in one T
empty and flag bit TXIF (PIR registers) is set. This inter-
rupt can be enabled/disabled by setting/clearing
enable bit TXIE (PIE registers). Flag bit TXIF will be
set, regardless of the state of enable bit TXIE and can-
not be cleared in software. It will reset only when new
data is loaded into the TXREG register. While flag bit
TXIF indicated the status of the TXREG register,
another bit TRMT (TXSTA register) shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
Steps to follow when setting up an Asynchronous
Transmission:
1.
2.
3.
4.
5.
6.
7.
Note 1: The TSR register is not mapped in data
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 16.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts trans-
mission).
LSb
0
2: Flag bit TXIF is set when enable bit TXEN
memory, so it is not available to the user.
TRMT
is set.
PIC18C601/801
Pin Buffer
and Control
SPEN
CY
), the TXREG register is
RC6/TX/CK pin
DS39541A-page 183
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