PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 232

• Manufacturer Part Number: PIC18C801-I/PT
• Description: IC PIC MCU ROMLESS 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/PT

• Core Size: 8-Bit
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 67
• Ram Memory Size: 1.5KB
• Cpu Speed: 6.25MIPS
• No. Of Timers: 4
• Program Memory Size: EXT
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801I/PT

PIC18C601/801
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS39541A-page 232
Before Instruction
After Instruction
Decode
REG
N
Z
REG
WREG
N
Z
Q1
=
=
=
=
=
=
=
register ’f’
Complement f
[ label ] COMF
0
d
a
N,Z
The contents of register ’f’ are com-
plemented. If ’d’ is 0 the result is
stored in WREG. If ’d’ is 1 the result
is stored back in register ’f’
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
1
1
COMF
( f )
Read
0001
Q2
13h
?
?
13h
0ECh
1
0
f
[0,1]
[0,1]
255
dest
REG
11da
Process
Data
Q3
f [,d [,a]]
ffff
destination
Advance Information
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
operation
operation
operation
Decode
PC Address
WREG
REG
After Instruction
If REG
If REG
No
No
No
Q1
Q1
Q1
PC
PC
register ’f’
operation
operation
operation
Compare f with WREG,
skip if f = WREG
[ label ] CPFSEQ
0
a
(f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
None
Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If 'f' = WREG
instruction is discarded and a NOP
is executed instead making this a
two-cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
NEQUAL
EQUAL
Read
0110
Q2
No
No
No
Q2
Q2
=
=
=
=
=
=
f
[0,1]
2001 Microchip Technology Inc.
by a 2-word instruction.
255
HERE
?
?
WREG;
Address (EQUAL)
WREG;
Address (NEQUAL)
CPFSEQ REG
:
:
001a
operation
operation
operation
Process
,
Data
then the fetched
No
No
No
Q3
Q3
Q3
ffff
f [,a]
operation
operation
operation
operation
Q4
No
No
No
No
Q4
Q4
ffff