PIC18C801-I/PT Microchip Technology, PIC18C801-I/PT Datasheet - Page 238

• Manufacturer Part Number: PIC18C801-I/PT
• Description: IC PIC MCU ROMLESS 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/PT

• Core Size: 8-Bit
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 67
• Ram Memory Size: 1.5KB
• Cpu Speed: 6.25MIPS
• No. Of Timers: 4
• Program Memory Size: EXT
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801I/PT

PIC18C601/801
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS39541A-page 238
Before Instruction
After Instruction
Decode
WREG
N
Z
WREG
N
Z
Q1
=
=
=
=
=
=
Inclusive OR literal with WREG
[ label ]
0
(WREG) .OR. k
N,Z
The contents of WREG are OR’ed
with the eight bit literal 'k'. The result
is placed in WREG.
1
1
literal ’k’
IORLW
Read
0000
Q2
9Ah
?
?
0BFh
1
0
k
255
IORLW k
1001
35h
Process
Data
Q3
WREG
kkkk
Advance Information
Write to
WREG
Q4
kkkk
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
RESULT =
WREG
N
Z
RESULT =
WREG
N
Z
Q1
=
=
=
=
=
=
register ’f’
Inclusive OR WREG with f
[ label ]
0
d
a
(WREG) .OR. (f)
N,Z
Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
1
1
IORWF
Read
0001
Q2
13h
91h
?
?
13h
93h
1
0
f
[0,1]
[0,1]
2001 Microchip Technology Inc.
255
RESULT, W
IORWF
00da
Process
Data
Q3
f [,d [,a]]
ffff
dest
destination
Write to
Q4
ffff