PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 169

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: IC PIC MCU FLASH 16KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 17-1:
TABLE 17-2:
The UOE signal toggles the state of the external trans-
ceiver. This line is pulled low by the device to enable
the transmission of data from the SIE to an external
device.
17.2.2.3
The PIC18FX455/X550 devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full-speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups. Figure 17-1
shows the pull-ups and their control.
17.2.2.4
External pull-up may also be used. The V
used to pull up D+ or D-. The pull-up resistor must be
1.5 kΩ (±5%) as required by the USB specifications.
Figure 17-3 shows an example.
FIGURE 17-3:
© 2007 Microchip Technology Inc.
VPO
VP
0
0
1
1
0
0
1
1
Note:
Microcontroller
PIC
VMO
VM
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
0
1
0
1
0
1
0
1
®
Internal Pull-up Resistors
External Pull-up Resistors
V
USB
D+
D-
DIFFERENTIAL OUTPUTS TO
TRANSCEIVER
SINGLE-ENDED INPUTS
FROM TRANSCEIVER
EXTERNAL CIRCUITRY
Single-Ended Zero
Single-Ended Zero
1.5 kΩ
Illegal Condition
Differential ‘0’
Differential ‘1’
High Speed
Low Speed
Bus State
Bus State
Error
Controller/HUB
USB
Host
pin may be
PIC18F2455/2550/4455/4550
Preliminary
17.2.2.5
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
17.2.2.6
The USB OE monitor provides indication as to whether
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
transceiver or when UCFG<6> = 1.
The USB OE monitoring is useful for initial system
debugging, as well as scope triggering during eye
pattern generation tests.
17.2.2.7
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
17.2.2.8
The PIC18FX455/X550 devices have a built-in 3.3V reg-
ulator to provide power to the internal transceiver and
provide a source for the internal/external pull-ups. An
external 220 nF (±20%) capacitor is required for stability.
The regulator is enabled by default and can be disabled
through the VREGEN Configuration bit. When enabled,
the voltage is visible on pin V
is disabled, a 3.3V source must be provided through
the V
transceiver is disabled, V
Note:
Note 1: Do not enable the internal regulator if an
USB
2: V
pin for the internal transceiver. If the internal
The drive from V
drive an external pull-up in addition to the
internal transceiver.
external regulator is connected to V
times, even with the regulator disabled.
Ping-Pong Buffer Configuration
USB Output Enable Monitor
Eye Pattern Test Enable
Internal Regulator
DD
must be greater than V
USB
is not used.
USB
USB
. When the regulator
is sufficient to only
DS39632D-page 167
USB
USB
at all
.