PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 423

• Manufacturer Part Number: PIC18F2550-I/SP
• Description: IC PIC MCU FLASH 16KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2550-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1536 B
• Interface Type: SPI, I2C, EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer2 .............................................................................. 135
Timer3 .............................................................................. 137
Timing Diagrams
© 2007 Microchip Technology Inc.
Oscillator .......................................................... 129, 131
Overflow Interrupt .................................................... 129
Resetting, Using a Special Event
Special Event Trigger (ECCP) ................................. 150
TMR1H Register ...................................................... 129
TMR1L Register ....................................................... 129
Use as a Real-Time Clock ....................................... 132
Associated Registers ............................................... 136
Interrupt .................................................................... 136
Operation ................................................................. 135
Output ...................................................................... 136
PR2 Register .................................................... 146, 151
TMR2 to PR2 Match Interrupt .......................... 146, 151
16-Bit Read/Write Mode ........................................... 139
Associated Registers ............................................... 139
Operation ................................................................. 138
Oscillator .......................................................... 137, 139
Overflow Interrupt ............................................ 137, 139
Special Event Trigger (CCP) .................................... 139
TMR3H Register ...................................................... 137
TMR3L Register ....................................................... 137
A/D Conversion ........................................................ 397
Acknowledge Sequence .......................................... 230
Asynchronous Reception (TXCKP = 0,
Asynchronous Transmission (TXCKP = 0,
Asynchronous Transmission, Back to Back
Automatic Baud Rate Calculation ............................ 246
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 252
Baud Rate Generator with Clock Arbitration ............ 224
BRG Overflow Sequence ......................................... 246
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 383
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision for Transmit and
Capture/Compare/PWM
CLKO and I/O .......................................................... 382
Clock Synchronization ............................................. 217
Layout Considerations ..................................... 132
Low-Power Option ........................................... 131
Using Timer1 as a Clock Source ..................... 131
Trigger Output (CCP) ....................................... 132
TX Not Inverted) .............................................. 251
TX Not Inverted) .............................................. 248
(TXCKP = 0, TX Not Inverted) ......................... 248
Normal Operation ............................................ 252
During Start Condition ..................................... 233
Condition (Case 1) ........................................... 234
Condition (Case 2) ........................................... 234
Condition (SCL = 0) ......................................... 233
Condition (SDA only) ....................................... 232
Condition (Case 1) ........................................... 235
Condition (Case 2) ........................................... 235
Acknowledge ................................................... 231
(All CCP Modules) ........................................... 385
PIC18F2455/2550/4455/4550
Preliminary
Clock/Instruction Cycle .............................................. 61
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 386
Example SPI Master Mode (CKE = 1) ..................... 387
Example SPI Slave Mode (CKE = 0) ....................... 388
Example SPI Slave Mode (CKE = 1) ....................... 389
External Clock (All Modes Except PLL) ................... 380
Fail-Safe Clock Monitor ........................................... 301
First Start Bit Timing ................................................ 225
Full-Bridge PWM Output .......................................... 155
Half-Bridge PWM Output ......................................... 154
High/Low-Voltage Detect Characteristics ................ 377
High-Voltage Detect (VDIRMAG = 1) ...................... 282
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 281
Master SSP I
Master SSP I
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 157
PWM Direction Change at Near
PWM Output ............................................................ 146
Repeated Start Condition ........................................ 226
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 253
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 198
SPI Mode (Slave Mode with CKE = 0) ..................... 200
SPI Mode (Slave Mode with CKE = 1) ..................... 200
SPP Write Address and Data for USB
SPP Write Address and Read Data for USB
SPP Write Address, Write and Read Data
Stop Condition Receive or Transmit Mode .............. 230
Streaming Parallel Port (PIC18F4455/4550) ........... 396
Synchronous Reception
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 390
C Bus Start/Stop Bits ............................................ 390
C Master Mode (7 or 10-Bit Transmission) ........... 228
C Master Mode (7-Bit Reception) ......................... 229
C Slave Mode (10-Bit Reception, SEN = 0) .......... 213
C Slave Mode (10-Bit Reception,
C Slave Mode (10-Bit Reception, SEN = 1) .......... 219
C Slave Mode (10-Bit Transmission) .................... 215
C Slave Mode (7-Bit Reception, SEN = 0) ............ 210
C Slave Mode (7-bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 1) ............ 218
C Slave Mode (7-Bit Transmission) ...................... 212
C Slave Mode General Call Address
(Master/Slave) ................................................. 394
(Master/Slave) ................................................. 394
SEN = 0, ADMSK 01001) ................................ 214
ADMSK = 01011) ............................................ 211
Sequence (7 or 10-Bit Address Mode) ............ 220
Auto-Restart Disabled) .................................... 160
Auto-Restart Enabled) ..................................... 160
100% Duty Cycle ............................................. 157
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 383
V
(4 Wait States) ................................................. 189
(4 Wait States) ................................................. 189
(No Wait States) .............................................. 189
(Master Mode, SREN) ..................................... 256
DD
Rise > T
2
2
C Bus Data ....................................... 392
C Bus Start/Stop Bits ........................ 392
PWRT
) ............................................ 49
DD
DS39632D-page 421
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