PIC18F2550-I/SP Microchip Technology, PIC18F2550-I/SP Datasheet - Page 190
![IC PIC MCU FLASH 16KX16 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2550-I/SP
Manufacturer Part Number
PIC18F2550-I/SP
Description
IC PIC MCU FLASH 16KX16 28DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F4550-IP.pdf
(430 pages)
8.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18F2550-I/SP
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2550-I/SP
Manufacturer:
MICROCHIP
Quantity:
2 100
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F4550-IP PDF datasheet #7
- PIC18LF2455-ISO PDF datasheet #8
- Current page: 190 of 430
- Download datasheet (7Mb)
PIC18F2455/2550/4455/4550
REGISTER 18-2:
18.1.2
The SPP has four control outputs:
• Two separate clock outputs (CK1SPP and
• Output enable (OESPP)
• Chip select (CSSPP)
Together, they allow for several different configurations
for controlling the flow of data to slave devices. When
all control outputs are used, the three main options are:
• CLK1 clocks endpoint address information while
• CLK1 clocks write operations while CLK2 clocks
• CLK1 clocks Odd address data while CLK2 clocks
Additional control options are derived by disabling the
CK1SPP and CSSPP outputs. These are enabled or
disabled with the CLK1EN and CSEN bits, respectively,
located in Register 18-2.
DS39632D-page 188
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5
bit 4
bit 3-0
CK2SPP)
CLK2 clocks data
reads
Even address data
CLKCFG1
R/W-0
CLOCKING DATA
CLKCFG1:CLKCFG0: SPP Clock Configuration bits
1x = CLK1 toggles on read or write of an Odd endpoint address;
01 = CLK1 toggles on write; CLK2 toggles on read
00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write
CSEN: SPP Chip Select Pin Enable bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port
CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port
WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states
•
•
0001 = 2 additional wait states
0000 = 0 additional wait states
CLKCFG0
R/W-0
SPPCFG: SPP CONFIGURATION REGISTER
CLK2 toggles on read or write of an Even endpoint address
W = Writable bit
‘1’ = Bit is set
R/W-0
CSEN
•
•
CLK1EN
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
18.1.3
The SPP is designed with the capability of adding wait
states to read and write operations. This allows access
to parallel devices that require extra time for access.
Wait state clocking is based on the data source clock.
If the SPP is configured to operate as a USB endpoint,
then wait states are based on the USB clock. Likewise,
if the SPP is configured to operate from the micro-
controller, then wait states are based on the instruction
rate (F
The WS3:WS0 bits set the wait states used by the SPP,
with a range of no wait states to 30 wait states, in multi-
ples of two. The wait states are added symmetrically to
all transactions, with one-half added following each of the
two clock cycles normally required for the transaction.
Figure 18-3 and Figure 18-4 show signalling examples
with 4 wait states added to each transaction.
18.1.4
The SPP data lines (SPP<7:0>) are equipped with
internal pull-ups for applications that may leave the port
in a high-impedance condition. The pull-ups are
enabled using the control bit, RDPU (PORTE<7>).
WS3
OSC
/4).
WAIT STATES
SPP PULL-UPS
R/W-0
WS2
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
WS1
R/W-0
WS0
bit 0
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