ATMEGA329P-20MU Atmel, ATMEGA329P-20MU Datasheet - Page 228

• Manufacturer Part Number: ATMEGA329P-20MU
• Description: IC MCU 32K 4X25 LCD CTRL 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA329P-16MU; ATMEGA329P-16MU

22.9.3
22.9.3.1
22.9.3.2
22.9.4
8021G–AVR–03/11
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
Table 22-5.
When an ADC conversion is complete, the result is found in these two registers. When ADCL is
read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
223.
ADPS2
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
15
15
R
R
–
7
0
0
R
R
7
0
0
R
7
–
0
ADC6
ADC8
ADC0
ACME
R/W
14
14
ADPS1
R
R
R
R
–
6
0
0
6
0
0
6
0
0
1
1
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
R
5
–
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
0
–
4
0
R
4
–
0
ADPS0
1
0
1
ADC3
ADC5
11
11
R
R
–
3
0
0
R
R
R
–
3
0
0
3
–
0
ATmega329P/3290P
ADTS2
ADC2
ADC4
R/W
10
10
R
R
–
2
0
0
R
R
–
2
0
0
2
0
”ADC Conversion Result” on
ADTS1
ADC9
ADC1
ADC3
Division Factor
R/W
R
R
9
1
0
0
R
R
9
–
1
0
0
1
0
128
32
64
ADTS0
ADC8
ADC0
ADC2
R/W
8
0
R
R
0
0
R
R
0
0
8
–
0
0
0
ADCSRB
ADCH
ADCL
ADCH
ADCL
228