ATMEGA329P-20MU Atmel, ATMEGA329P-20MU Datasheet - Page 244

• Manufacturer Part Number: ATMEGA329P-20MU
• Description: IC MCU 32K 4X25 LCD CTRL 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA329P-16MU; ATMEGA329P-16MU

8021G–AVR–03/11
Table 23-4.
• Bit 3 – Reserved
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in
Table 23-5.
The frame frequency can be calculated by the following equation:
Where:
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
LCDCD2
LCDPS2
1
1
1
0
0
0
0
1
1
1
1
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see
Table
LCDCD1
LCDPS1
LCD Prescaler Select (Continued)
LCD Clock Divide
23-5. This Clock Divider gives extra flexibility in frame rate selection.
0
1
1
0
0
1
1
0
0
1
1
LCDCD0
LCDPS0
1
0
1
0
1
0
1
0
1
0
1
Table 23-5 on page
divided by (D):
Output from
clk
clk
clk
f
Output from
Prescaler
frame
clk
Prescaler
LCD
LCD
LCD
LCD
/1024
/2048
/4096
1
2
3
4
5
6
7
8
=
/N
------------------------- -
(
K N D
244)
f
clk
⋅
LCD
Applied Prescaled LCD Clock Frequency
⋅
when LCDCD2:0 = 0, Duty = 1/4, and
ATmega329P/3290P
clk
)
LCD
1/4, gives a frame rate of:
= 32.768kHz, N = 16, and Duty =
Frame Rate = 64 Hz
520kHz
1MHz
2MHz
85.3Hz
51.2Hz
42.7Hz
36.6Hz
256Hz
128Hz
64Hz
32Hz
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