ATMEGA329P-20MU Atmel, ATMEGA329P-20MU Datasheet - Page 311

• Manufacturer Part Number: ATMEGA329P-20MU
• Description: IC MCU 32K 4X25 LCD CTRL 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA329P-16MU; ATMEGA329P-16MU

8021G–AVR–03/11
Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 27-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
XTAL1
PAGEL
XTAL1
DATA
DATA
BS1
XA0
XA1
BS1
XA0
XA1
OE
1. The timing requirements shown in
1. The timing requirements shown in
ing operation.
ing operation.Serial Downloading
Timing Requirements
ADDR0 (Low Byte)
LOAD ADDRESS
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
t
XLOL
t
OLDV
(1)
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 27-7
Figure 27-7
t
XLXH
t
BVDV
(i.e., t
(i.e., t
(HIGH BYTE)
LOAD DATA
ATmega329P/3290P
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
DATA (High Byte)
t
XLPH
Table 27-16 on page
, t
, t
LOAD DATA
XHXL
XHXL
, and t
, and t
t
OHDZ
t
PLXH
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
ADDR1 (Low Byte)
312, the pin
(1)
311