ATMEGA329P-20MU Atmel, ATMEGA329P-20MU Datasheet - Page 39

• Manufacturer Part Number: ATMEGA329P-20MU
• Description: IC MCU 32K 4X25 LCD CTRL 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA329P-16MU; ATMEGA329P-16MU

9.7
9.8
9.9
8021G–AVR–03/11
Power-save Mode
Standby Mode
Power Reduction Register
USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-
nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level
interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically
halts all generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in
When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 and/or the LCD controller are enabled, they will keep running during sleep.
The device can wake up from either Timer Overflow or Output Compare event from
Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2,
and the Global Interrupt Enable bit in SREG is set. It can also wake up from an LCD controller
interrupt.
If neither Timer/Counter2 nor the LCD controller is running, Power-down mode is recommended
instead of Power-save mode.
The LCD controller and Timer/Counter2 can be clocked both synchronously and asynchronously
in Power-save mode. The clock source for the two modules can be selected independent of
each other. If neither the LCD controller nor the Timer/Counter2 is using the asynchronous
clock, the Timer/Counter Oscillator is stopped during sleep. If neither the LCD controller nor the
Timer/Counter2 is using the synchronous clock, the clock source is stopped during sleep. Note
that even if the synchronous clock is running in Power-save, this clock is only available for the
LCD controller and Timer/Counter2.
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in six clock cycles.
The Power Reduction Register (PRR),
a method to stop the clock to individual peripherals to reduce power consumption. The current
state of the peripheral is frozen and the I/O registers can not be read or written. Resources used
by the peripheral when stopping the clock will remain occupied, hence the peripheral should in
most cases be disabled before stopping the clock. Waking up a module, which is done by clear-
ing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can
be used in Idle mode and Active mode to significantly reduce the overall power consumption. In
all other sleep modes, the clock is already stopped. Module shutdown can be used in IDLE
”PRR – Power Reduction Register” on page
”Clock Sources” on page
ATmega329P/3290P
”External Interrupts” on page 58
28.
43, provides
39