PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 35

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The MCU module is the heart of the PIC32MX3XX/4XX
Family processor. The MCU fetches instructions,
decodes each instruction, fetches source operands,
executes each instruction and writes the results of
instruction execution to the proper destinations.
3.1
• 5-stage pipeline
• 32-bit Address and Data Paths
• MIPS32 Enhanced Architecture (Release 2)
FIGURE 3-1:
© 2010 Microchip Technology Inc.
- Multiply-Accumulate and Multiply-Subtract
- Targeted Multiply Instruction
- Zero/One Detect Instructions
- WAIT Instruction
- Conditional Move Instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
Note 1: This data sheet summarizes the features
Instructions
MCU
2: Some registers and associated bits
PIC32MX MCU
Features
of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to Section 2. “MCU” (DS61113) of
the “PIC32MX Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
Resources
Processor
www.mips.com/products/cores/
32-bit-cores/mips32-m4k/#.
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
the
PIC32MX3XX/4XX
MCU BLOCK DIAGRAM
(RF/ALU/Shift)
Coprocessor
Execution
for
Core
System
Core
MDU
the
are
MIPS32
available
family
®
FMT
M4K
at:
of
®
Bus Interface
• MIPS16e
• Simple Fixed Mapping Translation (FMT)
• Simple Dual Bus Interface
• Autonomous Multiply/Divide Unit
• Power Control
• EJTAG Debug and Instruction Trace
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
- Bit field manipulation instructions
- 16-bit encoding of 32-bit instructions to
- Special PC-relative instructions for efficient
- SAVE & RESTORE macro instructions for
- Improved support for handling 8 and 16-bit
mechanism
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
- Maximum issue rate of one 32x16 multiply
- Maximum issue rate of one 32x32 multiply
- Early-in iterative divide. Minimum 11 and
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
- Extensive use of local gated clocks
- Support for single stepping
- Virtual instruction and data address/value
- breakpoints
- PC tracing with trace compression
EJTAG
for interrupt handlers
improve code density
loading of addresses and constants
setting up and tearing down stack frames
within subroutines
data types
interrupt latency
per clock
every other clock
maximum 34 clock latency (dividend (rs) sign
extension-dependent)
instruction)
Mgmt.
Power
Trace
TAP
PIC32MX3XX/4XX
®
Code Compression
Dual Bus I/F
Debug I/F
Off-Chip
Trace I/F
DS61143G-page 35