PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 68

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-20:
Legend:
Note
F000 OSCCON
F010 OSCTUN
F600
F610 RSWRST
0000 WDTCON
1:
2:
RCON
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
SYSTEM CONTROL REGISTERS MAP
31/15
ON
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
—
—
—
—
—
—
—
—
PLLODIV<2:0>
28/12
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
(1,2)
26/10
—
—
—
—
—
—
—
—
RCDIV<2:0>
NOSC<2:0>
CMR
25/9
—
—
—
—
—
—
—
VREGS
24/8
—
—
—
—
—
—
—
Bits
CLKLOCK
EXTR
23/7
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
SWR
22/6
—
—
—
—
—
—
LOCK
21/5
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
—
—
—
—
—
PBDIV<1:0>
SLEEP
19/3
CF
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
—
—
—
—
—
PLLMULT<2:0>
SOSCEN
17/1
BOR
—
—
—
—
—
—
WDTCLR 0000
OSWEN
SWRST
POR
16/0
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000