PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 71

• Manufacturer Part Number: PIC32MX460F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-25:
TABLE 4-26:
Legend:
Note
Legend:
Note
60C0
60D0
60E0
60F0
60C0
60D0
60E0
60F0
1:
1:
PORTD
PORTD
TRISD
TRISD
ODCD
ODCD
LATD
LATD
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORT D REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY
PORT D REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY
TRISD15
ODCD15
LATD15
31/15
31/15
RD15
—
—
—
—
—
—
—
—
—
—
—
—
TRISD14
ODCD14
LATD14
30/14
30/14
RD14
—
—
—
—
—
—
—
—
—
—
—
—
(1)
TRISD13
ODCD13
LATD13
29/13
29/13
RD13
—
—
—
—
—
—
—
—
—
—
—
—
TRISD12
ODCD12
LATD12
28/12
RD12
28/12
—
—
—
—
—
—
—
—
—
—
—
—
TRISD11
ODCD11
TRISD11
ODCD11
LATD11
LATD11
27/11
27/11
RD11
RD11
—
—
—
—
—
—
—
—
TRISD10
ODCD10
TRISD10
ODCD10
LATD10
LATD10
26/10
RD10
26/10
RD10
—
—
—
—
—
—
—
—
TRISD9
ODCD9
TRISD9
ODCD9
LATD9
LATD9
25/9
RD9
25/9
RD9
—
—
—
—
—
—
—
—
TRISD8
ODCD8
TRISD8
ODCD8
LATD8
LATD8
24/8
RD8
24/8
RD8
—
—
—
—
—
—
—
—
Bits
Bits
TRISD7
TRISD7
ODCD7
ODCD7
LATD7
LATD7
23/7
23/7
RD7
RD7
—
—
—
—
—
—
—
—
TRISD6
TRISD6
ODCD6
ODCD6
LATD6
LATD6
22/6
22/6
RD6
RD6
—
—
—
—
—
—
—
—
TRISD5
ODCD5
TRISD5
ODCD5
LATD5
LATD5
21/5
21/5
RD5
RD5
—
—
—
—
—
—
—
—
(1)
TRISD4
ODCD4
TRISD4
ODCD4
LATD4
LATD4
20/4
RD4
20/4
RD4
—
—
—
—
—
—
—
—
TRISD3
ODCD3
TRISD3
ODCD3
LATD3
LATD3
19/3
RD3
19/3
RD3
—
—
—
—
—
—
—
—
TRISD2
ODCD2
TRISD2
ODCD2
LATD2
LATD2
18/2
RD2
18/2
RD2
—
—
—
—
—
—
—
—
TRISD1
ODCD1
TRISD1
ODCD1
LATD1
LATD1
17/1
RD1
17/1
RD1
—
—
—
—
—
—
—
—
TRISD0
TRISD0
ODCD0
ODCD0
LATD0
LATD0
16/0
16/0
RD0
RD0
—
—
—
—
—
—
—
—
0000
FFFF
0000
xxxx
0000
xxxx
0000
0000
0000
0FFF
0000
xxxx
0000
xxxx
0000
0000