AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 17

• Manufacturer Part Number: AT89C51ED2-RDTUM
• Description: IC 8051 MCU FLASH 64K 64VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51ED2-RDTUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 60MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: UART, SPI
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT89
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 50
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: VQFP
• For Use With: AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7. Enhanced Features
7.1
7.1.1
4235K–8051–05/08
X2 Feature
Description
In comparison to the original 80C52, the AT89C51RD2/ED2 implements some new features,
which are
The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called
‘X2’ provides the following advantages:
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 7-1
the XTAL1 ÷ 2 to avoid glitches when switching from X2 to STD mode.
switching mode waveforms.
• X2 option
• Dual Data Pointer
• Extended RAM
• Programmable Counter Array (PCA)
• Hardware Watchdog
• SPI interface
• 4-level interrupt priority system
• Power-off flag
• ONCE mode
• ALE disabling
• Some enhanced features are also located in the UART and the Timer 2
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically the operating frequency by 2 in operating
• Increase CPU power by 2 while keeping same crystal frequency.
and idle modes.
:
shows the clock generation block diagram. X2 bit is validated on the rising edge of
AT89C51RD2/ED2
Figure 7-2
shows the
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