AT89C51ED2-RDTUM Atmel, AT89C51ED2-RDTUM Datasheet - Page 72

IC 8051 MCU FLASH 64K 64VQFP

AT89C51ED2-RDTUM

Manufacturer Part Number
AT89C51ED2-RDTUM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51ED2-RDTUM

Core Processor
8051
Core Size
8-Bit
Speed
60MHz
Connectivity
SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
50
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
50
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Cpu Family
AT89
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Total Internal Ram Size
2KB
# I/os (max)
50
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
VQFP
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

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17. Interrupt System
Figure 17-1. Interrupt Control System
72
AT89C51RD2/ED2
EXF2
KBD IT
SPI IT
INT0
INT1
PCA IT
TF0
TF1
TF2
RI
TI
The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard
interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1.
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register
High register
with each combination.
Individual Enable
(Table 17-5
IE0
IE1
and
IPH, IPL
Table
(Table 17-4
17-6) shows the bit values and priority levels associated
Global Disable
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
3
0
and
Table
17-6). This register also contains a global
(Table
17-7) and in the Interrupt Priority
High Priority
Interrupt
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
4235K–8051–05/08

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